Speaker
Mr
Marc Majoral
(CTTC)
Description
Currently the Agency is using space-qualified GNSS receivers based on ASIC solutions (in particular, the AGGA-family) integrated in ad-hoc instruments (receivers). Such receivers provide outstanding measurement quality required for POD (Precise Orbit Determination) performed on ground, but at the cost of high price and power consumption. In order to address the needs of low cost missions (eg: cubesats, microsat) there is a need for reducing the cost of space GNSS receivers. There is a need as well to have a higher configurability and flexibility to adapt or update, in a straightforward way, the GNSS space receiver to new missions, applications, platforms and, eventually, future GNSS signals.
GNSS software-defined space receivers running on consumer based powerful SoC (System on Chip) could represent a viable alternative to ASIC based solutions. Recent studies and roadmaps show that these chips can be used in space. GNSS signal processing is a heavy task, particularly for high speed correlation functions and (optional) digital filtering at baseband. SoC merging both FPGA and microprocessors (ARM) allow the implementation of high demanding correlation tasks in FPGA, while the remaining part of the processing can be done in the microprocessor.
The focus of our activity is the implementation of a GNSS Space Receiver using a Xilinx Zynq 7000 SoC. The Zynq 7000 contains a dual-core Cortex-A9 processor mated with an Artix-7 based programmable logic.
The GNSS Space Receiver is based on the open source GNSS-SDR software-defined receiver. The GNSS-SDR takes care of all the digital signal processing, performing signal acquisition and tracking of the available satellite signals, decoding the navigation message and computing the observables needed by positioning algorithms, which ultimately compute the navigation solution. The software is designed to facilitate the inclusion of new signal processing techniques, offering an easy way to measure their impact in the overall receiver performance
The ARM cores run the GNSS-SDR software-defined receiver. In order to run the GNSS-SDR software on real time, some functions are implemented in the FPGA part of the SoC (the Programming Logic). These functions are implemented as hardware accelerators that implement the most computationally intensive operations of the GNSS receiver.
The hardware accelerator modules are implemented in the form of FPGA IP cores. The importance of FPGA IPs has grown over the years. They ease the reusability and the integration of the VHDL modules and they are a common way of distributing VHDL modules. The hardware accelerators are implemented as IPs that use the IP-XACT specification, which is widely used for packaging, integrating and reusing IP within design tool flows.
In this work we present a description of the GNSS Space receiver and how it is implemented in the Zynq SoC.
Summary
Implementation of a GNSS Space Receiver on a Xilinx Zynq-7000 SoC. The GNSS Space Receiver is implemented using the open source software-defined GNSS-SDR receiver and custom-made hardware accelerators in the PL (Programming Logic). The hardware accelerators implement the most computationally instensive operations of the receiver.
Primary author
Mr
Marc Majoral
(CTTC)
Co-author
Dr
Javier Arribas
(Centre Tecnologic de Telecomunicacions de Catalunya (CTTC))
