9–11 Apr 2018
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
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From eFPGA cores to RHBD SoC FPGA

11 Apr 2018, 09:00
1h
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speaker

Mr JOEL LE MAUFF (NanoXplore)

Description

NanoXplore is a privately owned fabless company based in France, created by veterans of semiconductor industry with roughly 30 years experience in the design, test and debugging of e-FPGA cores. Thanks to that background, NX has been awarded a contract by European Space Agencies, ESA and CNES, to develop and to industrialize Radiation Hardened Sram-based FPGA devices under both ESCC and DLA quality standards in order to increase the FPGA offer. The 1st part of the presentation will start fixing the Space FPGA market size and will explain why NanoXplore is a credible solution for the Space sector. Next we will present Strategical choices in term of technology nodes, supply-chain as well as design approaches. Especially, we will address RHBD (Radiation Hardening By Design) approach targeting the lowest Soft-Error rate in order NX RH Sram-based FPGA devices becoming suitable for Critical Spaceborne applications. The 2nd part of the presentation will cover the NX product roadmap. We will first address the Low-End FPGA named NG-Medium introduced on the Space market for months, addressing features vs competition, packaging and QA level solutions vs ECSS classes as well as for sure Radiation performances and Qualification planning. Next, we will switch to the Mid-End FPGA product named NG-Large which will offer Europe a competitive solution against most complex RH FPGA devices present on the market. Last but not least, we will open the future with our High-End SoC FPGA which will become the 1st RH 28nm FPGA device, offering World-Wide customers a Flight-Model solution for Spaceborne applications validated at Breadboard level with XILINX & INTEL PSG COTS solutions. Last, we will conclude and open the Questions & Answers session.

Summary

NanoXplore will address the RHBD Sram-based FPGA roadmap, starting from the NG-Medium, presenting the industrial status, going up the RHBD SoC FPGA.

Primary author

Mr JOEL LE MAUFF (NanoXplore)

Co-author

Mr Edouard LEPAPE (NanoXplore)

Presentation materials