Speaker
Johannes Both
(Jena-Optronik)
Description
Thanks to its robust design and accurate measurements, the Jena-Optronik RVS© LIDAR sensors are the most frequently used rendezvous- and docking sensors for ISS resupply by the European ATV, Japanese HTV and the US-American “Cygnus” transport vehicle built by Orbital ATK. The RVS sensor is limited, though, to rendezvous and docking with cooperative targets, i.e. targets equipped with retro-reflector elements.
For future applications like on-orbit servicing, space debris removal or planetary landing, a more powerful 3D imaging LIDAR system is required. Following the ESA sponsored technology development activity “ILT” (Imaging LIDAR Technology) and the DLR project “LiQuaRD” (LIDAR Qualification for Rendezvous and Docking), a concept for a new powerful, yet compact and cost-effective LIDAR system was developed to both replace the previous RVS sensor and enable additional mission scenarios: the RVS3000 product family.
The RVS3000 product family currently consists of two LIDAR versions: The RVS3000 for cooperative targets using retroreflectors (e.g. ISS) and the 3D imaging version RVS3000-3D, capable of performing relative navigation with uncooperative (diffuse) targets in scenarios ranging from Satellite Servicing to Debris Removal.
Current developments at Jena-Optronik for the RVS3000-3D are aimed at integrating LIDAR image processing techniques for real-time 6 degrees of freedom (6DOF) Pose Estimation with uncooperative targets. Such integration is intended to work with the sensor through a standardized interface in order to allow the use of both third party SW and proprietary algorithms developed by Jena-Optronik.
Those algorithms require a high performance computing hardware, thus, a standard spacegrade FPGA or processor is not sufficient anymore. Making a step forward towards high-performance in orbit data-processing, Jena-Optronik has developed a universal multi-purpose hardware module which is already preselected for multiple missions. The module utilizes the Microsemi RTG4 FPGA as main computing unit. It is supported by multiple persistent and high-speed memory modules. Communication is realized by up to 6 SpW ports which can run, thanks to the RTG4 integrated SpW clock recovery circuits, at up to 200 Mbps each.
A main challenge for RTG4-based designs is the PCB mounting technology for the CCGA1557 package with 1 mm pitch. Jena-Optronik is currently qualifying a solder process utilizing a low-CTE PCB material together with mechanical support structures for the FPGA package. The concept has already been developed for SMT qualification of the Xilinx Virtex 5 FPGA, which was successfully completed in 2015.
The second part of the presentation will focus on experience made during FPGA design process. Jena-Optronik will provide feedback on different aspects of the tool chain, RTG4 related design restrictions and Microsemi support. Finally, a summary of the design results of the current project will be presented.
Primary author
Johannes Both
(Jena-Optronik)
Co-author
Mr
Edgar Kolbe
(Jena-Optronik)
