Speaker
Mr
Joao Oliveira
(Spin.Works)
Description
The work presented in this article is the product of an activity with the objective of further develop and flight test visual based navigation (VBN) and hazard detection and avoidance (HDA) algorithms to serve the needs of future Mars and other planetary missions and raise them to a technology readiness level (TRL) of 5 (“critical function verification in a relevant environment”).
The Zynq-7020 SoC was selected as the hardware platform for development. Being a dual-core architecture, one CPU was fully dedicated to the VBN, enabling the development of a fast and efficient software design, whilst leaving the second CPU dedicated to flight and mission control systems. The co-processing FPGA was programmed to handle both the required on-board sensor interfaces and the processing IP blocks that compose the VBN hardware accelerators.
This work presents the performance results comparing the CPU-only version of VBN with the CPU+FPGA approach, taking into account a target frame rate of 10Hz. Performance is measured not only in terms of processing speed, but also in terms of algorithm performance degradation and impact on the navigation accuracy.
Primary author
Mr
Joao Oliveira
(Spin.Works)
Co-authors
Carlos Posse
(Spin.Works)
Mr
Francisco Camara
(Spin.Works)
Mr
Jose Canilho
(Spin.Works)
Mr
Tiago Hormigo
(Spin.Works)
