Speaker
Mr
Andrzej Cichocki
(Centrum Badan Kosmicznych PAN)
Description
Safety-critical digital applications often require calculating the probability of system failure. Existing tools for verification of FPGA-based designs in terms of susceptibility to SEUs/SETs base mainly on fault injection methods, that require numerous runs in order to get proper statistics and are not exhaustive. Run-time of post P&R simulations may significantly limit complexity of analysed designs (like SST), while hardware accelerated fault-injection needs specialized hardware (FTUNSHADES). On the other hand, formal verification methods can only evaluate subsets (InFault or Questa Formal) of implemented
fault mitigation techniques (eg. hardware & information redundancy only). The talk proposes a new combined approach of a "formal simulation" in fuzzy-logic domain, that can be especially helpful to determine probability of specific failures and covers all forms of redundancy (eg. oversampling, scrubbing). It maybe also used to find weak points (most fault contributive) in the design and compare different mitigation techniques. The method has been implemented as a software that takes post-synthesis netlist as an input (ProASIC3) which can be accompanied with a stimulus. Preliminary results of execution for simple designs with fault mitigation implemented are to be presented.
Summary
This talk addresses a new method of assessment of fault mitigation techniques employed in digital designs using fuzzy-logic domain simulations.
Primary author
Mr
Andrzej Cichocki
(Centrum Badan Kosmicznych PAN)
