Speaker
Mr
David Hernandez Exposito
(Instituto de Astrofísica de Andalucía - CSIC)
Description
In this work we present a novel FPGA implementation of the Image Data Compression standard proposed by the Consultative Committee for Space Data Systems (CCSDS-IDC 122.0-B) aboard the Polarimetric Helioseismic Imager instrument of the ESA’s Solar Orbiter mission (SO/PHI).
The SO/PHI telemetry constraints enforce the use of specific strategies for on-board data reduction, analysis, and compression. In this context, our CCSDS-IDC compressor is aimed at processing images of different sizes, performing lossless compression of at least a factor two during nominal operation modes, and lossy compression with several compression factors in other specific modes.
The proposed CCSDS-IDC implementation is in-flight reconfigured within one of the two Virtex-4 QPro-VSX55 FPGA devices included in the SO/PHI Digital Processing Unit. The embedded architecture consists of two functional blocks, namely, the Discrete Wavelet Transform (DWT) and the Bit Plane Encoder (BPE) cores. The DWT core is accelerated by means of a light multi-processor architecture combined with a smart structure of buffers. On the other side, the BPE core is carefully pipelined to perform one pixel per clock cycle.
This architecture performs lossless and lossy compression of 2048 x 2048 images with full dynamic range of 16 bit/pixel in less than 3 seconds, which implies a factor 30 acceleration with respect to a LEON-3FT processor. The final implementation uses around 50% of FPGA logic and 65% of block-RAM memory elements in contrast to other hardware implementations that use larger FPGA devices or external memory resources.
To our knowledge, it is the first in-flight reconfigurable FPGA implementation of a CCSDS-IDC-compliant algorithm for an ESA mission, which introduces important improvements regarding time and use of resources.
Summary
In this work we present a novel FPGA implementation of the Image Data Compression standard proposed by the Consultative Committee for Space Data Systems (CCSDS-IDC 122.0-B) aboard the Polarimetric Helioseismic Imager instrument of the ESA’s Solar Orbiter mission (SO/PHI). This solution, based on a light multi-processor architecture combined with an efficient ad-hoc Bit Plane Encoder core, speeds up by a factor 30 the execution time of a LEON-3FT processor. Additionally, it has been optimized for a low resource occupancy.
Primary author
Mr
David Hernandez Exposito
(Instituto de Astrofísica de Andalucía - CSIC)
Co-authors
Dr
David Orozco Suárez
(Instituto de Astrofísica de Andalucía - CSIC)
Dr
José Carlos Del Toro Iniesta
(Instituto de Astrofísica de Andalucía - CSIC)
Mr
José Luis Ramos Mas
(Instituto de Astrofísica de Andalucía - CSIC)
Dr
Juan Pedro Cobos Carrascosa
(Institute of Astrophysics of Andalusia)
Dr
Manuel Rodríguez Valido
(Universidad de La Laguna)
