Speakers
Mr
Klemen Bravhar
(ESA)Mr
Stephan van Beek
(MathWorks)
Description
The FPGAs for space are growing in complexity and performance and the design time is shortening. There are several high-level synthesis approaches that aim to help FPGA designers increase their productivity.
The objective of this work is to assess the MATLAB/Simulink high-level design flow, by using 2 applications from the specification to the deployment into different FPGA platforms.
For the assessment, two FPGA design flows have been used: the high-level FPGA MATLAB/Simulink and the RTL VHDL coding. The applications chosen are Vision algorithms, as they are highly parallelizable and therefore use all advantages of FPGA (pipelines, DSP, Memory) to reach real time data handling/ manipulation. In this manner we developed Green Screen and Edge Detection (Sobel filter) FPGA applications. In the MATLAB/ Simulink design flow we used the HDL coder/Vision HDL Toolbox to produce VHDL.
In both FPGA design flows, the VHDL of the applications has been simulated to verify the functionality and then we executed the implementation on Xilinx and NanoXplore FPGAs. Several metrics have been obtained at the end of both design flows - such as resources used, achieved frequencies, overall development effort - in both FPGA technologies.
Primary author
Mr
Klemen Bravhar
(ESA)
Co-authors
Mr
David Merodio Codinachs
(ESA)
Mr
Stephan van Beek
(MathWorks)
