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SEFUW: SpacE FPGA Users Workshop, 4th Edition

9–11 Apr 2018
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
PLEASE READ ME: public presentations (made available by the presenters) posted on website - for the presentations not available and/or password protected, a public version was not made available by the presenters.

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Session

Design Flow

9 Apr 2018, 11:30
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Conveners

Design Flow

  • David Merodio Codinachs (ESA)

Design Flow

  • Lucana Santos (ESA)

Design Flow

  • David Dangla (CNES)

Presentation materials

There are no materials yet.

  1. 8. UVVM - Universal VHDL Verification Methodology. Setting a standard for VHDL testbenches
    Mr Espen Tallaksen (Bitvis)
    09/04/2018, 11:30
    For an FPGA design we all know that the architecture – all the way from the top to the micro architecture – is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench. Most FPGA designs are split into stand-alone modules – for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities...
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  2. 15. Evaluation of MATLAB/Simulink and RTL VHDL HDL environment
    Mr Klemen Bravhar (ESA), Mr Stephan van Beek (MathWorks)
    09/04/2018, 15:10
    The FPGAs for space are growing in complexity and performance and the design time is shortening. There are several high-level synthesis approaches that aim to help FPGA designers increase their productivity. The objective of this work is to assess the MATLAB/Simulink high-level design flow, by using 2 applications from the specification to the deployment into different FPGA platforms. For...
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  3. 41. QUEENS-FPGA: Quality Evaluation of European New SW for the BRAVE FPGA
    Mr David Gonzalez-Arjona (GMV Aerospace and Defence)
    11/04/2018, 10:00
    GMV is the prime contractor of QUEENS-FPGA project which stands for “QUality Evaluation of European New SW for brave FPGA”. The BRAVE project supported by ESA and CNES provided very promising European SRAM-based FPGAs for Space, a good roadmap that will allow Europe to avoid restrictions on access to non-European technologies and FPGAs. GMV will present the preliminary conclusions of NG-MEDIUM...
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  4. 40. High-Performance Benchmarking of the European NG-MEDIUM FPGA
    Dr George Lentaris (National Technical University of Athens, Greece)
    11/04/2018, 10:25
    “Quality Evaluation of European New SW for the BRAVE FPGA” (QUEENS-FPGA) is an ongoing ESA activity for the assessment and improvement of the programming tools of the new rad-hard NG-MEDIUM FPGA. Given BRAVE's primary target, i.e., high-performance applications, it becomes imperative to test the tool and device with computationally demanding benchmarks suitable for space missions, such as...
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  5. 25. An ECSS-Q-ST-60-02C compliant verification flow for scientific projects
    Mr Marcin Darmetko (Centrum Badan Kosmicznych PAN (Space Research Centre))
    11/04/2018, 10:50
    Verification of a space project is a complex and time-consuming task due to requirements for high reliability and extensive documentation. Unexpected changes to design are likely to happen in scientific projects, often forcing the whole process to be repeated. Because of these reasons, automation is highly desirable in space FPGA development. The aim of the presentation is to show that...
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