Conveners
Tools Vendors
- Florent Manni (DC/TV/IN)
Tools Vendors
- Florent Manni (DC/TV/IN)
Dr
Reuven Dobkin
(vSync Circuits)
09/04/2018, 12:10
Inter clock domain crossings inside multiple clock domain design must be treated carefully in order to eliminate synchronization failures and assure design reliability. For space applications, the reliability assurance is crucial, calling for employment of state-of-the art design integration and verification techniques.
The problem is exacerbated by the fact that the synchronization bugs...
Mr
Scott Calkins
(Blue Pearl Software. Inc)
09/04/2018, 12:35
ASIC and System on Chip (SoC) design and verification practices have traditionally been much more rigorous than that of their FPGA counterparts. Mandated by large non-recurring engineering (NRE) fees associated with the manufacturing setup, design teams set up robust verification methodologies that are rigorously followed to avoid errors that could cause an expensive re-spin. With NRE fees in...
Mr
Philipp Jacobsohn
(Synopsys)
09/04/2018, 14:00
Deploying FPGAs in high-assurance applications makes it necessary to protect the device against malfunction. SEU mitigation and error monitoring circuitry is a mandatory prerequisite for any FPGA design used in high radiation environments. Designing SEU-tolerant circuits can be done in manual or automated ways by introducing design techniques such as triple-mode-redundancy and safe...
Mr
Simone Catenacci
(Mentor, a Siemens Business)
09/04/2018, 14:25
Emerging design methodologies and increasingly complex FPGAs are creating a need for new approaches to verification to keep pace. As a result, the balance is shifting as more FPGA users want and need to adopt modern verification practices in order to be competitive but don't always know where to start or find the cost/risk too great to embark on. This session will discuss themes in the FPGA...
Mr
Mark Handover
(Mentor, A Siemens Business)
09/04/2018, 14:50
In recent years, Formal verification has moved beyond a tool solely for use by experts and into the mainstream. Now, targeted formal apps’ are lowering the barrier to entry for formal, enabling its use in automated design checking, clock domain crossing analysis and coverage closure to name a few.
This session will briefly discuss a range of formal apps’ available before focusing on one...
