SEFUW: SpacE FPGA Users Workshop, 4th Edition

from Monday, 9 April 2018 (09:30) to Wednesday, 11 April 2018 (17:00)
European Space Research and Technology Centre (ESTEC) (Newton 1 and 2)

        : Sessions
    /     : Talks
        : Breaks
9 Apr 2018
10 Apr 2018
11 Apr 2018
AM
09:30 --- Registration and Early Morning Networking Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division ---
10:00 Welcome - Mr David Merodio Codinachs (ESA) Mr David Dangla (CNES)   (Newton 1 and 2)
Slides
10:30
Industrial Experiences -Mr David Dangla (CNES) (until 11:30) (Newton 1 and 2)
10:30 FPGA experience and SoC design methodology at Airbus Defence & Space. - Mr Ottmar Ried (Airbus Defence & Space GmbH)   (Newton 1 and 2)
Slides
10:50 Jena-Optronik Experience Summary on Microsemi RTG4 designs - Johannes Both (Jena-Optronik)   (Newton 1 and 2)
Slides
11:10 SpaceFibre, Spectrometer and Camera: Some applications on the RTG4 FPGA - Prof. Steve Parkes (University of Dundee)   (Newton 1 and 2)
Slides
11:30
Design Flow -Mr David Merodio Codinachs (ESA) (until 12:10) (Newton 1 and 2)
11:30 UVVM - Universal VHDL Verification Methodology. Setting a standard for VHDL testbenches - Mr Espen Tallaksen (Bitvis)   (Newton 1 and 2)
Slides
08:50 --- SEFUW Intro - Opening Remarks ---
09:00
FPGA Vendors -Mr Agustin Fernandez-Leon (ESA) (until 10:00) (Newton 1 and 2)
09:00 Xilinx On-Orbit Reconfigurable Kintex UltraScale FPGA Technology for Space - Mr Daniel Elftmann (Xilinx)   (Newton 1 and 2)
Slides
10:00
Industrial Experiences -Mr Agustin Fernandez-Leon (ESA) (until 10:20) (Newton 1 and 2)
10:00 First Design-In Experiences of Xilinx's, 20 nm, Kintex UltraScale KU060 for Space Applications and 16 nm UltraScale+ RFSoC for Ground Segment - Dr Rajan Bedi (Spacechips Ltd)   (Newton 1 and 2)
Slides
10:20
Radiation -Mr Christian POIVEY (ESA) (until 11:10) (Newton 1 and 2)
10:20 Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA - Mr Thomas Lange (IROC Technologies)   (Newton 1 and 2)
Slides
10:45 Ultra-High Energy Heavy Ions radiation tests on COTS FPGAs at CERN: results for Microsemi ProASIC3 and Xilinx Zynq all-programmable SoC - Dr Antonios Tavoularis (European Space Agency)   (Newton 1 and 2)
Slides
11:10 --- Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division ---
11:40
FPGA Vendors -Mr Agustin Fernandez-Leon (ESA) (until 12:40) (Newton 1 and 2)
11:40 Microsemi RTG4 Radiation Tolerant FPGAs: Radiation and Qualification Update - Mr Ken O'Neill (Microsemi)   (Newton 1 and 2)
Slides
08:50 --- SEFUW Intro - Opening Remarks ---
09:00
FPGA Vendors -Mr David Dangla (CNES) (until 10:00) (Newton 1 and 2)
09:00 From eFPGA cores to RHBD SoC FPGA - Mr JOEL LE MAUFF (NanoXplore)   (Newton 1 and 2)
Slides
10:00
Design Flow -Mr David Dangla (CNES) (until 11:10) (Newton 1 and 2)
10:00 QUEENS-FPGA: Quality Evaluation of European New SW for the BRAVE FPGA - Mr David Gonzalez-Arjona (GMV Aerospace and Defence)   (Newton 1 and 2)
Slides
10:25 High-Performance Benchmarking of the European NG-MEDIUM FPGA - Dr George Lentaris (National Technical University of Athens, Greece)   (Newton 1 and 2)
Slides
10:50 An ECSS-Q-ST-60-02C compliant verification flow for scientific projects - Mr Marcin Darmetko (Centrum Badan Kosmicznych PAN (Space Research Centre))   (Newton 1 and 2)
Slides
11:10 --- Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division ---
11:40
Fault Tolerance Methodologies and Tools -Mr David Merodio Codinachs (ESA) (until 13:00) (Newton 1 and 2)
11:40 Permanent Fault Handling in SRAM-based FPGAs - Mr Florian Rittner (Friedrich-Alexander-Universität Erlangen-Nürnberg)   (Newton 1 and 2)
Slides
12:00 Fuzzy-logic simulation based approach to modelling of fault propagation in FPGAs. - Mr Andrzej Cichocki (Centrum Badan Kosmicznych PAN)   (Newton 1 and 2)
Slides
12:20 Reprogrammable Flash-based FPGA on EUCLID mission - Prof. Luca Sterpone (Politecnico di Torino) Dr Raoul Grimoldi (OHB ITALIA)   (Newton 1 and 2)
Slides
12:40 Advancement on the Analysis and Mitigation of SETs on Flash-based FPGAs - Dr Sarah Azimi (Politecnico di Torino)   (Newton 1 and 2)
Slides
PM
12:10
Tools Vendors -Mr Florent Manni (DC/TV/IN) (until 13:00) (Newton 1 and 2)
12:10 Multiple-clock Domain FPGA Designs: Challenges and Solutions - Dr Reuven Dobkin (vSync Circuits)   (Newton 1 and 2)
Slides
12:35 RTL Analysis and CDC Analysis for Maximum Design Efficiency and Quality - Mr Scott Calkins (Blue Pearl Software. Inc)   (Newton 1 and 2)
Slides
13:00 --- Networking Luncheon ---
14:00
Tools Vendors -Mr Florent Manni (DC/TV/IN) (until 15:10) (Newton 1 and 2)
14:00 Build and Debug Highly Reliably FPGA-based Designs - Mr Philipp Jacobsohn (Synopsys)   (Newton 1 and 2)
Slides
14:25 Advanced Verification for FPGAs - Mr Simone Catenacci (Mentor, a Siemens Business)   (Newton 1 and 2)
Slides
14:50 Exhaustively Verify SEU Mitigation Techniques Using Formal Verification - Mr Mark Handover (Mentor, A Siemens Business)   (Newton 1 and 2)
Slides
15:10
Design Flow -Ms Lucana Santos (ESA) (until 15:30) (Newton 1 and 2)
15:10 Evaluation of MATLAB/Simulink and RTL VHDL HDL environment - Mr Stephan van Beek (MathWorks) Mr Klemen Bravhar (ESA)   (Newton 1 and 2)
Slides
15:30
FPGA Vendors -Ms Lucana Santos (ESA) (until 15:50) (Newton 1 and 2)
15:30 FUSIO RT: A New Space Modular Computer Core based on Nanoxplore NG-Medium FPGA - Mr Pierre-Xiao WANG (3D PLUS) Mr Pierre-Eric Berthet (3D PLUS)   (Newton 1 and 2)
Slides
15:50
Fault Tolerance Methodologies and Tools -Ms Lucana Santos (ESA) (until 16:30) (Newton 1 and 2)
15:50 Analysis and Mitigation of Single Event Upsets in Configuration Memory of Xilinx Kintex7 SRAM-based FPGA - Dr BOYANG DU (Politecnico di Torino)   (Newton 1 and 2)
Slides
16:10 Fault injection for space: FT-Unshades2 updates, experiences and roadmap - Prof. Hipólito Guzmán-Miranda (Universidad de Sevilla)   (Newton 1 and 2)
Slides
16:30 --- Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division ---
17:00
Demo Session and Cocktail Reception sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division -Mr David Merodio Codinachs (ESA) Mr David Dangla (CNES) (until 18:45) (Newton 1 and 2)
12:40
Reconfiguration -Mr AURELIEN ODOUNDE (CNES) (until 13:00) (Newton 1 and 2)
12:40 Modern On-Board-Processing based on FPGAs for Flexible Satellite Communication - Mr Florian Rittner (Friedrich-Alexander-Universität Erlangen-Nürnberg)   (Newton 1 and 2)
Slides
13:00 --- Networking Luncheon ---
14:00
Reconfiguration -Mr AURELIEN ODOUNDE (CNES) (until 15:20) (Newton 1 and 2)
14:00 FPGA Based Multithreading for On-Board Processing - Mr Pasquale Lombardi (Syderal) Mr Andrea Guerrieri (EPFL) Mr Bilel Belhadj (Syderal)   (Newton 1 and 2)
Slides
14:40 Controlling Concurrent Change in Aerospace Electronics - Dr Björn Fiethe (IDA TU Braunschweig)   (Newton 1 and 2)
Slides
15:00 Overlay Architectures for Space Applications - Dr Jose Sousa (IPbloq)   (Newton 1 and 2)
Slides
15:20
FPGAs: High Performance -Ms Lucana Santos (ESA) (until 16:20) (Newton 1 and 2)
15:20 Review and comparison of design methodologies and hardware implementations on FPGA technologies. Case study: CCSDS compression algorithms for multispectral and hyperspectral images - Mr Yúbal Barrios (IUMA/ULPGC) Dr Antonio Sánchez (IUMA/ULPGC)   (Newton 1 and 2)
Slides
15:40 Image compression on reconfigurable FPGA for the SO/PHI space instrument - Mr David Hernandez Exposito (Instituto de Astrofísica de Andalucía - CSIC)   (Newton 1 and 2)
Slides
16:00 Implementation of Visual Based Navigation in a CPU-FPGA architecture for planetary landing - Mr Joao Oliveira (Spin.Works)   (Newton 1 and 2)
16:20 --- Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division ---
16:50
FPGAs: High Performance -Ms Lucana Santos (ESA) (until 17:10) (Newton 1 and 2)
16:50 Implementation of a GNSS Space Receiver on a Zynq - Mr Marc Majoral (CTTC)   (Newton 1 and 2)
Slides
17:10
Industrial Experiences -Mr David Merodio Codinachs (ESA) (until 17:30) (Newton 1 and 2)
17:10 A Comparison of 65 nm Space-Grade and COTS FPGAs : RTG4 vs. V5QV vs. NG-MEDIUM vs. NG-LARGE vs. IGLOO2 vs. SmartFusion2 - Dr Rajan Bedi (Spacechips Ltd)   (Newton 1 and 2)
Slides
17:30 --- Round Table and Wrap up ---
18:45 --- SEFUW Dinner ---
13:00 --- Networking Luncheon ---
14:00
Industrial Experiences -Mrs Silvia Moranti (ESA) (until 16:00) (Newton 1 and 2)
14:00 Using Open-source Spacewire and RMAP IPs in the PLATO Router and Data compressor Unit (RDCU) - Dr Jorge Tonfat (Space Research Institute / Austrian Academy of Sciences)   (Newton 1 and 2)
Slides
14:20 Virtex5QV - Device & High Speed Interfaces Feedbacks - Mr DANILO LAMONACA (Thales Alenia Space Italy)   (Newton 1 and 2)
14:40 Use of FPGAs in a scientific instrument development process: processing, testbenchs, simulators - Mr Damien Rambaud (IRAP CNRS)   (Newton 1 and 2)
Slides
15:00 Evaluation of a New Mass Memory Controller Architecture on Space-Grade FPGAs - Mr Lei Jia (Institute of Computer and Network Engineering (IDA), TU Braunschweig, Braunschweig, Germany)   (Newton 1 and 2)
Slides
15:20 Comparison between Microsemi RTG4 and Xilinx SIRF - Mr Felix Vermersch (SERMA)   (Newton 1 and 2)
15:40 Radiation Testing and End User Validation of the BRAVE NG-Medium FPGA - Mr Luis Berrojo (Thales Alenia Space in Spain)   (Newton 1 and 2)
16:00 --- Concluding remarks and closure ---