12-16 November 2018
Europe/Amsterdam timezone

New Developments in FPGA: SEUs and Fail-Safe Strategies

14 Nov 2018, 11:00
Newton 1-2 (ESA/ESTEC)

Newton 1-2


Keplerlaan 1, 2200 AG Noordwijk The Netherlands
Mitigation and hardening Mitigation and Hardening


Mrs Melanie Berg (NASA - GSFC)


Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being implemented. They range from weaker EDAC circuits that save area and power to strong mitigation strategies that come as a great expense to the system. Regarding FPGA and ASIC EDAC insertion, there is no “one-solution-fits-all.” The user must be aware of plethora of concerns. As an example, each FPGA device-type requires a different mitigation strategy for various reasons. This presentation will focus on the susceptibilities of a variety of FPGA types and ASICs in the avionics and space environment. In addition, the user will be provided information on what are the optimal mitigation strategies per FPGA and ASIC. Internal device component mitigation versus system level mitigation will also be discussed.

Primary author

Mrs Melanie Berg (NASA - GSFC)

Presentation Materials