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Description
The DARE65 Phase-Locked Loop (PLL) is implemented in a 65nm process, operating at 1.2V using a P-sub/Twin-Well commercial CMOS technology. In the PLL, the loop itself is composed of a Voltage-Controlled Oscillator (VCO) based on a ring oscillator, a programmable Charge-Pump (CP) synchronized with a loop divider, a Phase Frequency Detector (PFD) and a 2nd order Low Pass Filter (LPF). Besides the loop, there are three more sub-circuits in the PLL: an input divider, an output divider and a lock detector. The output divider generates a clock signal with a frequency from 6.25MHz – 1200MHz according to the configuration of the three dividers.
The PLL has less than 15ps of period jitter under environmental conditions without Single Event Transient (SET) strikes and 5.1mA of power consumption in the worst case. When radiation-hardened techniques are determined, the power consumption should also be evaluated, otherwise current-starving techniques such as redundancy techniques and increase of driving strength may cause degradation of the general PLL performance.
In the DARE65 PLL design, the radiation-hardening techniques have been considered circuit by circuit. The VCO is implemented based on redundancy techniques, which are firstly averaging-by-redundancy, secondly a large capacitor for voltage-current converter and thirdly triple modular redundancy (TMR) for the ring oscillator. In contrast to the ring oscillator, the voltage-current converter is an analog circuit and it is necessary to apply hardening techniques different from the ring oscillator. In the CP, a series resistor is added at the output in order to attenuate SET-caused fluctuations on the control voltage of the VCO. The radiation hardening is unnecessary for the LPF because it is implemented with MOS capacitance and the active region is connected to the ground node in this PLL design. TMR is applied to the three dividers and lock detector while the PFD is implemented based on radiation-hardened digital cells that have strong driving strength. Compared to the other digital sub-circuits, the PFD state-machine is too complex to use triple modular redundancy, because an additional circuit is necessary for the TMR-based state machine to correct a corrupted state from a SET strike.
For mitigation of Single-Event Latch-up (SEL) and Total Ionizing Dose (TID), diffusion guard-rings are employed to provide SEL hardening and to lower inter-device leakage current for TID conditions up to 100krad.
This radiation-hardened PLL is designed to guarantee less than 280ps of timing error caused by a 60MeV.cm²/mg SET strike. This timing error is verified for a 1200MHz output clock, meaning that the rising edge of the output clock experiences 280ps of shift during the 833.333ps period, which is less than 120° phase deviation. The output divider can be programmed to 1, 2, 4, 8, 16, 32, 64 and 128 of division ratio and the VCO has 800MHz – 1200MHz output frequency range. Due to these circuit performances, users can obtain a wide-range of SET-immune clock signals from the DARE65 PLL. A tape-out of the DARE65 PLL along with other DARE65 IPs is currently under preparation and its performance will be validated by radiation test in the near future.
