Speaker
Dr
Gildas Leger
(IMSE)
Description
This brief presents the experience of integrating two high-performance Data Converter IPs, an ADC and a DAC, in a single rad-hard test-chip. A system-level perspective is taken, underlining the importance of Design-for-Testability (DfT) structures and tuning structures for debugging purposes and achieving first-time right silicon.
Modeling the interactions between domains (PCB, package, analog and digital) is also highlighted as a key to success, particularly for high performance circuits operating at the limits of technology.
Primary authors
Dr
Gildas Leger
(IMSE)
Dr
Antonio Gines
(IMSE)
Dr
Eduardo Peralias
(IMSE)
Dr
Jose Miguel Mora
(IMSE)
Dr
Antonio Ragel
(IMSE)
