Speaker
Description
As soon as FinFET technology was shown to be a viable alternative to planar technology for nodes lower than 28nm, the radiation community has begun tests to characterize available technology from manufacturers such as Intel, Samsung, Global Foundries, TSMC and radiation testing and service providers [1][2][3][4]. A reduced SEE sensitivity has been observed due to lower carrier collection in the FinFET structure. TID effects are qualitatively similar to planar technology with a small threshold voltage shift and an increase of subthreshold current and STI induced leakage current. As FinFET are majority carriers displacement damage is not anticipated to be important. But Single Defect or Defect Clusters induced by protons or heavy ions in a nuclear collision may be important to consider in 12nm technology. The influence of a single defect depends upon its position in the channel and may modify the electrical characteristics of a single FinFET.
To elaborate on these aspects, this paper will include a global survey of radiation effects on FinFET technology. The synthesis of available results published in selected reviews (Nuclear Science, …), published in conferences (NSREC, RADECS, IRPS, SELSE..) or other public sources will present the sensitivity to total ionizing dose (TID), displacement damage (DD) and single event effects (SEE).
SEE EFFECTS
As an example, the SEE evaluation of the Kintex Ultrascale+ FPGA from XILINX (manufactured with TSMC’s 16nm FinFET process) promises a good behavior regarding SEE.
However, SEL [8] was observed with a relatively high cross section of 2E-3 on power supplies VccAux=1.8V and VccINT=0.85V. The origin of this sensitivity is probably related to the small depth of the STI in FinEFT technologies and should be investigated further.
TID EFFECTS
For Global Foundry 14nm, King et al [9] has studied TID effects on FinFET transistors, SRAM cells and Ring Oscillators for high and low Vth transistors showing only small variation of Ioff below 100krad. IdsOn/Idsoff ratio is reduced from 1E6 at D=0 to 1E2-1E3 at 1 Mrad. Worst case bias conditions are identified. High threshold voltage devices show a smaller response linked to differences in process.
The available results seem to suggest that FinFET technologies are a good match to the requirements of space applications. However, many of the studies focus on the ground-level reliability, relevant for today’s industry’s hot topics such as automotive. The evaluation of the SEE effects in harsh environments dominated by heavy ions or protons is complicated by the particular 3-D structure of the FinFET cells and the fine-grained sensitive device volumes. The paper will present simulation and analysis methods and tool frameworks that can accurately predict SEE performance for complex cells. Particularly, State-of-the-Art (SOTA) EDA frameworks working at TCAD or transistor-level abstraction levels can produce a very exhaustive picture of the device weaknesses and strengths for analog, digital or mixed-mode designs: cross-section of internal cell transistors with a very fine spatial granularity for each possible state of the cell, particle characteristics and impact angle and so on.
Experimental and simulation results can provide invaluable, actionable data that can be used effectively during the hardening phase of the selected technologies or libraries. In addition to non-destructive Single Event Transient/Upset analysis and hardening, a special consideration will be provided to Single Event Latch-ups as previous tests on the UltraScale+ FPGA shown that this type of event can significantly affect the behaviour of devices implemented on FinFET nodes.
In conclusion, FinFET technologies show a great promise for space applications, provided that their behavior is well studied and critical SEE events such as SELs are managed.
