Speaker
Description
When exposed to radiation, semiconductor components exhibit various single-event effect (SEE) and total ionization dose (TID) behavior. Notably, parametric drifts, latch-up and ?functional disruptions? (SEL and SEFI, resp.). These effects have been studied and dealt with in the industry for several decades.
The obvious approach for operating in the space environment, namely the use of radiation-hardened semiconductor processes and components, is not always viable, for technical, economic and possibly other reasons. This statement has become even more important over the last decade, as the demand for launching nano and micro-satellites has increased considerably.
Consequently, there are numerous reasons why it may be advantageous to use generic, off-the-shelf components (COTS) in spacecraft and other high-reliability settings. In short, as long as the operation of the device or component in question can accommodate intermittent loss of function (caused by SEEs) and is therefore not required to have a 100% uptime, then using COTS components in combination with suitable protection against SEL-related over-currents is an effective solution.
A Dynamic Latch-up Current Protection ASIC design project has been carried out by nSilition in collaboration with the Technical Center (ESTEC) of ESA.
As a first step, the device was specified from functional and implementation points of view. Then a feasibility study was carried out in order to select, among several candidates, which CMOS or SOI process could be most suitable platform. A 0.18?m SOI fabrication process was selected and a short list of the devices that will be used on the design was generated.
A test chip was designed initially. One objective was to ascertain the effect of TID on the principal parameters of particular devices. Next, all the functional blocks implemented on the test chip (bandgap, bias circuitry, OTP and OTP programming, charge pump, digital cells, IOs, main switch and its control circuitry), some in multiple versions, were tested against effects due to TID and SEEs. Expected behavior was observed in many cases. The blocks exhibiting suitable behavior were then selected for the design of the LUCA chip.
The LUCA chip contains all blocks necessary to operate the device according to the functional specifications.
A first-order temperature compensated bandgap and together with biasing circuitry provides voltage and current references. These blocks are reused or enhanced from the test chip.
The Power Management Unit (PMU) conditions the supply voltage received on either the VDD or on the VIN pin (two different supply schemes are possible). All the necessary internal supply voltages are partitioned into several supply domains, some at 3.3V, others at 1.8V, typical. The presence of multiple supply domains is part of the on-chip power integrity strategy. It limits the risk that a block with a periodically varying power consumption disturbs the supply of a precise sensor interface or of the ADC. A charge pump, needed to efficiently operate the main switch, is used to create voltages above the VIN voltage.
An internal 10MHz oscillator provides the main clock. An external 10MHz clock can also be used instead (through the CLK pin), in case any residual noise due to the clock of LUCA must be specifically controlled and timed. This may be the case, e.g., when the load being protected by the LUCA is a highly sensitive sensor.
The main switch and all its control and sensing circuitry implement the LUCA?s current control and latch-up current detection functionalities. A ?HIGH/LOW? pin provides a low latency control of the latch-up detection value. This will accommodate applications requiring a fast transition time between a stand-by mode (LOW) and an active mode (HIGH), so that the current limiting protection function does not need to be set for only the maximum active mode current.
Over-voltage and over-temperature circuits are blocks necessary for avoiding potentially destructive conditions. A resistor-based sensing circuity arrangement allows the LUCA to be pre-conditioned at start-up. The value of some external resistors is examined and provides a way to program the threshold of LUCA in case no SPI master is available (standalone mode).
Finally, a telemetry feature is built around a 10b ADC. Using an OBC connected to the SPI interface, various values and status parameters can be read-out at any time: input voltage, load current, temperature, current status of the LUCA, number of remaining automatic restarts after over-current, alert before latching, etc. Once latched (protection triggered), OBC intervention or cycling of the stand-by pin is necessary to restart and power the load again.
Cold spare IOs are used for interfacing all the digital signals to the board. This allows unused/unpowered LUCA devices to be connected to the SPI bus lines and other digital controls. An OTP provides all the necessary trimming and pre-programming in order to achieve satisfactory precision and avoid yield losses due to fabrication process tolerance.
The nSilition?s digital library (tested on the test chip) was made fully synthesizable and automatically place-and-routable for industrial grade digital tools. The layout floorplan was worked out, taking into account package cavity size, thermal considerations, and package parasitic resistances. In particular, the IN-OUT current path constrains the floorplan of the chip.
Finally, the first LUCA prototype chip was taped-out in January, 2020. Packaged samples of first silicon have been received March 2021. First validated engineering samples will be available by August 2021 and tested radiation tolerant devices by the end of 2021.
