12–14 Nov 2019
ESA/ESTEC
Europe/Amsterdam timezone

Brave Large processing board

12 Nov 2019, 17:05
25m

Speaker

Mr Aurélien Odounde  (CNES)

Description

In the frame of CNES R&D program, a new generic processing board based on the NanoXplore NG-Large SoC is being developed.

This board, evolution of the itar-free CPUGEN board commercialized by EREMS, will see the “Gaisler GR712 processor + ATMEL AT280 FPGA” couple replaced by the NG-Large SoC for more power efficiency and more versatility.

The form factor will be adapted to match the space VPX format while trying to still cope with the ITAR free requirement. The board will benefit from high speed link to connect with external high throughput equipment or accelerator board.

Presentation materials