Speaker
Description
Two new ECSS standards will soon supersede the still in effect ECSS-Q-ST-60-02C (2008) “ASIC and FPGA development”:
- ECSS-E-ST-20-40 “ASIC, FPGA and IP Core engineering”
- ECSS-Q-ST-60-02C Rev.1 “ASIC, FPGA and IP Core product assurance”
These two new standards will finish going through Public Review in Oct 18th 2022, therefore anyone can review the drafts and submit request for changes until then. After that date the standard drafts will undergo final corrections and improvements in order to be published by ECSS as soon as possible (end of 2022 we hope). An ECSS WG integrated by more than 35 experts from industry, ESA, CNES and DLR, has worked meticulously during 3 years to produce these two complementary engineering and PA standards. These standards will be made applicable for developments of ASICs, FPGAs and IP Cores to be used in ESA projects and technology R&D activities. Engineering and PA requirements have been separated in these two books. This promotes that the supervision of the chip or IP development is done in parallel by engineering technical officers and PA officers from both, the customer and the supplier side. My presentation will summarize the main differences in content and format with respect to the old standard. Some important differences are the new and improved requirements related to HW-SW co-engineering, mixed-signal ASICs, development and re-use of IP Cores, flexibility in the development flows, new chip engineer-friendly terminology for key milestone reviews, default pre-tailoring according to “criticality category” and the type of “DEVICE” (digital ASIC, analog ASIC, FPGA or IP Core) to be developed.
