Speaker
Description
A modular design approach is a fundamental concept for developing high-complexity FPGA designs. Both design and verification effort can be reduced by partitioning system design requirements into functionally isolated modules, using standard interconnects between these modules to tie the system together. IP core reuse of proven modules and modules with flight heritage can reduce both mission development risk and mission operation risk.
Existing FPGA interconnect standards such as APB, AXI3, AXI4 and AXI-Lite have been designed primarily for SoC implementation, utilising wide buses and a large number of control signals to provide both high performance and flexibility, which is well suited to SoC implementations typically containing a processor system or complex DMA engines. However, both FPGA resource usage overhead and increased verification effort of the interconnect infrastructure reduce the suitability to designs that do not require these features, such as the CO2M MAP instrument which is entirely FPGA based.
In this presentation we present TAS-UK’s leightweight IP InterConnect (IPIC) concept and illustrate how this has been used to develop a complex flight project in a very short timeframe. The CO2M MAP instrument contains many IP cores typical of an FPGA used for control of a complex instrument: EEPROM, stepper motor control, DDR2, heater control, thermistor acquisition, TMTC over MIL-STD-1553 and science data over SpaceWire. This is in addition to control of the CIS120 sensor control IP that is the heart of the MAP instrument concept. All of these modules have been developed with simple IPIC interfaces that are then connected via the IPIC interconnect infrastructure.
Further to this, the IPIC concept provides easy memory-mapped access to all registers in the design. This is very useful for patch/dump access during both AIT and Flight, but also allows a flexible TMTC handling process to be developed for MAP. The MAP TC handling and TM acquisition uses a pre-loaded table of IPIC read/write commands across the MAP memory address space to action the TC or collect the TM set, allowing both TC execution and the TM collection set to be updated in flight if required.
The IPIC has allowed the MAP design team to not only develop and test these modules in isolation, but also to build scripts for automatic generation of IPIC connection infrastructure VHDL and automatic ICD documentation generation, ensuring that the design and the documentation are true representations of each other with minimal FPGA designer effort. The auto-generation tools can also generate VHDL packages for register address and bit field constants used for system level simulation, allowing registers to be added or address maps changes to be made without requiring test benches to be rewritten. Further to this, a standardised interface allows unit testing of each module to be carried out easily, using a generic IPIC unit test harnesses in place of the IPIC interconnect and the VUnit framework to manage test execution and tracking.
