SEFUW: SpacE FPGA Users Workshop, 5th Edition

Session

Design Flow

14 Mar 2023, 12:00

Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Conveners

Design Flow

• Florent Manni (CNES (DSO/TB/ET))
• Alberto Urbón Aguado (Telespazio for ESA)

Design Flow

• Alberto Urbón Aguado (Telespazio for ESA)
• Florent Manni (CNES (DSO/TB/ET))

5. Getting Started with OSVVM, VHDL's #1 Verification Methodology (SynthWorks Design)

Mr Jim Lewis (SynthWorks Design Inc.)

14/03/2023, 12:00

Design Flow

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and scripting API that simplify your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex...

37. Verification of a CCSDS121-based data compression IP core through fuzzing (U. Palmas de Gran Canaria / U. Autonoma Barcelona)

Antonio J. Sanchez (Universidad de las Palmas de Gran Canaria)

14/03/2023, 12:25

Design Flow

System-level design commonly employs building blocks, also denoted as soft IP cores, to conform complex developments. This is also a trend in the space industry to save costs and development time.
Every IP must pass through a verification and validation process before being integrated in a larger design to ensure a proper system behaviour. In order to ensure the functional correctness of the...

18. UVVM: A game changer for efficient FPGA verification and good FPGA quality (EmLogic)

Espen Tallaksen (EmLogic AS)

16/03/2023, 14:25

Design Flow

Verification is critical for an acceptable FPGA quality, but unfortunately, achieving a good FPGA quality is often very time-consuming and difficult. However, with a good testbench architecture, the workload could be reduced significantly and at the same time really improve the quality.

UVVM provides the best VHDL testbench architecture possible and also **allows a unique reuse...

23. Verification Strategy of Multi-FPGA Systems (Airbus CRISA)

Mrs Isabel Hidalgo (AIRBUS CRISA)

16/03/2023, 14:50

Design Flow

FPGAs are getting more complex with each product generation.
Nowadays systems require, in most cases, many complex FPGAs which are connected and interchange data and control between them in a robust and reliable way.

Not only the functionality of the system must be proved, but also its robustness, its functional behaviour under stress conditions by intensive tests to verify bandwidth...