Conveners
Fault Tolerance Methodologies and Tools
- Filomena Decuzzi
- Alberto Urbón Aguado (Telespazio for ESA)
Fault Tolerance Methodologies and Tools
- Filomena Decuzzi
- David Merodio Codinachs (ESA)
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Luca Sterpone (Politecnico di Torino)15/03/2023, 11:40Fault Tolerance Methodologies and Tools
Field Programmable Gate Array (FPGA) devices are a golden core of many applications in space and avionic fields where reliability is an important concern. In this presentation, we present a set of EDA tools for the evaluation and mitigation of radiation-induced Single Event Effects (SEEs) on FPGAs. The tools are compatible with COTS and Rad-Hard FPGAs with SRAM and Flash -based Configuration...
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Mr Fabio Benevenuti (Universidade Federal do Rio Grande do Sul (UFRGS))15/03/2023, 12:05Fault Tolerance Methodologies and Tools
The adoption of modern commercial grade SRAM-Based FPGAs, unencumbered by export restrictions, allows to take advantage of its growing computing power and reduced cost, volume, mass and power consumption for space applications ranging from control tasks to signal processing, from software-defined radio to machine learning, both in the “traditional-space” and the “new-space”.
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The use of SRAM... -
Martin J. Losekamm (Technical University of Munich)16/03/2023, 10:20Fault Tolerance Methodologies and Tools
We present the ongoing development of a Payload Data Processor for small satellites based on a Xilinx Kintex UltraScale FPGA. To increase the flexibility and reliability of the system, we use a Vorago Technologies ARM Cortex-M4 as a companion microcontroller. The controller configures the FPGA, can be used as an external scrubber, and controls the payload’s data acquisition electronics. A...
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Klemen Bravhar16/03/2023, 10:45Fault Tolerance Methodologies and Tools
A Field Programmable Gate Array (FPGA) is becoming an essential component of a satellite since it can support various digital functionalities. However, like any other integrated circuit, an FPGA is not immune to a Single Event Upset (SEU) caused by charged radiation particles. Most optimal architectures to test the FPGA fabric in a harsh radiation environment are simple chain architectures...
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