14–16 Mar 2023
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Presentations available

Comparison of COTS FPGA in Middle Earth Orbit and Nuclear Laboratory Environment (MEO- FPGA) (University of Maribor)

16 Mar 2023, 10:45
25m
Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Erasmus High Bay

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Fault Tolerance Methodologies and Tools Fault Tolerance Methodologies and Tools

Speaker

Klemen Bravhar

Description

A Field Programmable Gate Array (FPGA) is becoming an essential component of a satellite since it can support various digital functionalities. However, like any other integrated circuit, an FPGA is not immune to a Single Event Upset (SEU) caused by charged radiation particles. Most optimal architectures to test the FPGA fabric in a harsh radiation environment are simple chain architectures (one chain link has one LUT and D-Flip op) with different SEE error mitigation techniques. The proposed research uses such architectures on an experimental device, and Commercial of The Shelf (COTS) SRAM-based FPGA serves as an experimental device. The research aims to evaluate the COTS FPGA in a chaotic outer space and controlled laboratory radiation environment. The first part of the COTS FPGA evaluation will take place in outer space as part of the TRISAT-R satellite mission at an altitude of 6000 km. At the same time, the most suitable facilities for evaluating the COTS FPGA in a nuclear laboratory environment is CERN’s CHARM facility with Mixed Field radiation particles.
The results gained from the TRISAT-R satellite mission in MEO and nuclear laboratories will help us correlate and evaluate an SRAM FPGA behavior in harsh radiation environment. Device Under Test (DUT) is a Commercial-Off-The-Shelf (COTS) SRAM-based Xilinx Artix-7 FPGA technology. The target device tests three different FPGA images stored in NAND flash memory. The differences in FPGA images are in applied Tripel Modular Redundancy (TMR) mitigation technique.
During the tests we will measure number of errors on the chain’s data path, number of successful and failed reconfiguration of the FPGA, occurred Latch-up in Artix-7 FPGA and power consumption.
Up to this date we have concluded tests in CHARM nuclear laboratories with, where we proved that a COTS FPGA can be successfully reconfigured in harsh radiation environment. Furthermore, longer the experiment was exposed to radiation particles, the power required to configured FPGA increased. On the subject of errors on the chain's data path, the data path without TMR had the higher number of errors compare to the other two data paths which had similar number of errors. The second part of the research takes place in Earth’s orbit as part of TRISAT-R mission. This part of the research is still in progress since we are waiting for a time slot which will allow us to do measurements described above. Our plan is to conduct measurements until the end of February.

Primary author

Klemen Bravhar

Co-author

Dr Iztok Kramberger

Presentation materials