EDHPC 2025 - 2nd European Data Handling & Data Processing Conference

Topics

Satellite End-to-end data handling and processing architectures

• On-Board data processing architectures

  A1

• On-board data handling architectures

  A2

• ADHA - Advanced Data Handling Architecture

  A3

• Reconfigurable Data System Architectures

  A4

• Distributed processing architectures

  A5

  Distributed computing of data and signal processing

• Signal processing chain architectures

  A6

• Lessons learnt

  A7

Avionics and data handling systems for platform, launchers, optical & RF payloads

• On-Board Computer (OBC) units, Remote Terminal Units (RTU), Mass Memory units, Instrument Control units (ICU)

  B1

• High Performance Hardware Data and Signal Processing unit/module,

  B2

  o High throughput electronics for Radar back-ends, Radiometer back-ends, Instrument Front End Electronics
  o High throughput electronics for transparent and regenerative processors for Satellite Communication, Intersatellite and TT&C units

• Software Defined Radios

  B3

• Use of digital and mixed-signal components in OBC / OBDP and in data/signal processing systems (Reference Designs)

  B4

  Multicore processors, GPUs, FPGAs, DSPs, memories, full custom processor ICs,SoC, SiP, DAC, ADC

• Use of COTS in OBC / OBDP and signal processing systems

  B5

  Selection, radiation test results, mitigation technics in designs

• Validation & verification, testing, qualification, simulation, modelling of complex systems

  B6

• Lower-class mission, smallsat and cubesat data handling equipment

  B7

• Processor simulators/emulators

  B8

• Software development platforms/toolchains for the new generation of processors (including FPGAs) - compilers, debuggers, etc.

  B9

• Qualification of low-level software libraries (e.g. OpenMP)

  B10

Buses, networks & protocols

• Protocol developments of SpaceWire, SpaceFibre, CAN-Bus, Ethernet, other protocols

  C1

• Software building blocks for higher level protocols

  C2

• Validation & verification

  C3

  Simulation suites, Test equipment, approaches, and standards

• Components

  C4

  Embedded interfaces in processors/FPGAs, Switches, routers, SerDes, (optical) transceiver, connectors, harness

• Wireless Technologies

  C5

OBDP (On-Board Data and Signal Processing)

• Device Benchmarks (Multicore processors, GPUs, FPGAs)

  D1

• Developments in On-Board Data Processing Frameworks, Architectures and Building Blocks

  D2

  Parallel processing frameworks (OpenMP, OpenCL), Hardware acceleration of processing tasks, Heterogeneous processing systems, FPGA IP and HLS

• On-board Data Processing Algorithms and Implementations

  D3

• On-board processing applications for Multi- and Hyperspectral image processing, Visual navigation, Data reduction

  D4

• On-board Signal Processing Algorithms for RF applications such as SDR, 5G/6G gNb, AIS, ADS-B, Beamforming, Modems, PNT, Positioning, Synthetic aperture radar (SAR) processing, Radio interferometer processing

  D5

  Implementations of On-board Signal Processing Algorithms for RF applications (DSP SW, FPGA IP and HLS, etc)

• AI and Machine learning for on-board data processing

  D6

  Data Analysis (classification, segmentation, selection), datasets for training of on-board AI, Efficient Neural Networks, Software tools and FPGA IP for machine learning inference, Fault-tolerance in deep learning algorithms, applications for RF Payloads and Instruments, like signal intelligence, anomaly detection, spectrum allocation, cognitive radar, network orchestration

• Validation & verification of hardware and software implementation of On-Board Data & Signal Processing algorithms and functions.

  D7