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EDHPC 2025 - 2nd European Data Handling & Data Processing Conference

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EDHPC 2025

The second European Data Handling & Data Processing Conference – EDHPC 2025 – will be held from the 13th to the 17th of October 2025 in Elche, Spain. It is organised by the European Space Agency (ESA), with the support of the local tourist office. Find the latest information on the official website.

The full paper submission is now open, please find instructions here. The deadline for final paper, filled copyright form and presentation submission is the 15th of September. The deadline for the presenter conference registration is the 30th of June, please follow the instructions on the official website.

EDHPC IEEE LaTeX template
EDHPC2025 Conference Copyright Form.docx
IEEE EDHPC Word Template.docx
EDHPC Organising Committee
  • Sunday 12 October
    • 18:00
      Pre-opening cocktail Altamira Castle (Archelogical Museum of Elche)

      Altamira Castle (Archelogical Museum of Elche)
  • Monday 13 October
    • EDHPC Plenary: Welcome and Keynotes
    • 10:40
      Coffee Break
    • EDHPC Plenary: Keyontes Afternoon
    • 12:30
      Lunch
    • EDHPC Tutorial: ADHA 101
      Conveners: David Steenari (ESA), Kostas Marinis (ESA)
      • 1
        ADHA 101: ADHA introduction, overview, navigating the data pack, and how to propose an ADHA ESA activity
        Speaker: David Steenari (ESA)
      • 2
        ADHA 101: ADHA Architecture
        Speakers: Julian Bozler (Airbus Space Systems), Robin Franz (Airbus Defence and Space)
      • 3
        ADHA 101: ADHA Module Designs
        Speaker: Mr Dario Pascucci (Thales Alenia Space)
      • 4
        ADHA 101: Technologies for thermal management in electronics units
        Speaker: Stephane Lapensee (ESA)
    • EDHPC Tutorial: BrainChip part 1
      Conveners: Alf Kuchenbuch (Brainchip), Gilles Bezard (Brainchip)
    • EDHPC Tutorial: Mathworks: AI-based Spacecraft Pose Estimation on ANY FPGA - part I
      Conveners: Lucas Garcia (Mathworks), Stephan van Beek (MathWorks)
    • EDHPC Tutorial: Radiation Testing
      Conveners: Dr Maris Tali (ESA), Melanie Berg (Space R2 LLC), Pierre Maillard (AMD, INc.)
      • 5
        Radiation Effects in FPGAs and SoCs: Adapting to a Changing Technological Landscape

        Abstract
        FPGAs and SoCs are well-suited for complex designs and evolving algorithms in terrestrial and space applications, especially compared to ASICs. This tutorial covers SRAM and non-volatile FPGA architectures, their evolution into modern Adaptive SoCs, and mechanisms behind Single Event Effects (SEE) and Total Ionizing Dose (TID). We’ll also explore how Functional Safety, RAS, and AI/ML applications have impacted SEE metrics, mitigation, and testing. It includes error classifications, mitigation strategies, testing methods, and results. The final section addresses challenges and solutions for next-gen markets, including telecom, automotive, data centers, avionics, and defense sectors.

        Biography
        Dr. Pierre Maillard leads the Radiation Effects & RAS Solutions team at AMD’s Adaptive Embedded Computing Group (AECG), focusing on the architecture, development, and validation of radiation-tolerant FPGA and SoCs solutions for markets such as Telecom, Avionics, Automotive, Datacenters, AI, Defense and Space. He has more than 20 issued patents in radiation effects on electronics and is a Senior Member of IEEE, with over 20 publications and presentations in industry-leading conferences and journals. Dr. Maillard holds M.S. and Ph.D. degrees in Electrical Engineering from Vanderbilt University and an M.S. from the University of Montpellier II.

        Speaker: Pierre Maillard (AMD, INc.)
      • 6
        Radiation Testing Tutorial Presentation 2
        Speaker: Melanie Berg (Space R2 LLC)
      • 7
        Radiation Testing Tutorial Roundtable
        Speakers: Dr Maris Tali (ESA), Melanie Berg (Space R2 LLC), Pierre Maillard (AMD, INc.)
    • 16:00
      Coffee Break
    • EDHPC Tutorial: Brainchip part 2
      Conveners: Alf Kuchenbuch (Brainchip), Gilles Bezard (Brainchip)
    • EDHPC Tutorial: HW accelerators and Harmonisation
      Conveners: Kostas Marinis (ESA), Lucana Santos Falcon (European Space Agency)
    • EDHPC Tutorial: Mathworks: AI-based Spacecraft Pose Estimation on ANY FPGA - part II
      Convener: Adam Taylor (Adiuvo Engineering Training ltd)
    • EDHPC Tutorial: Satellite Radio Frequency payloads and Instruments
      Conveners: Dr Adem Coskun (ESTEC), Max Ghiglione (ESA)
    • 18:00
      Opening cocktail
  • Tuesday 14 October
    • ADHA Plenary
      Conveners: David Steenari (ESA), Kostas Marinis (ESA)
      • 8
        ADHA (Advanced Data Handing Architecture) Development Status and Roadmap
        Speakers: David Steenari (ESA), Kostas Marinis (ESA)
      • 9
        ESA EOP ADHA presentation
        Speaker: Josep Rosello (ESA/ESTEC/EOP-SFT)
      • 10
        ADHA-3: the expansion of a modular standard
        Speaker: Julian Bozler (Airbus Space Systems)
      • 11
        ADHA System Study Expansion: Missions use cases analysis, additional modules and ADHA-3U specifications, Data/SW Interfaces and EGSE standardization
        Speaker: Mr Dario Pascucci (Thales Alenia Space)
      • 12
        OHB ADHA presentation
        Speaker: Jon Caudepon (OHB)
    • On-board Processing Architectures
      Conveners: Dr Maris Tali (ESA), Oskar Flordal (Unibap AB)
      • 13
        Reshaping the Earth-Observation value chain through AI-eXpress powered satellite-as-a-service
      • 14
        Satellite-as-a-Service Architecture for ML Edge Computing on Heterogeneous Processing Platforms

        This paper presents a Satellite-as-a-Service (SaaS) architecture designed to enable flexible and efficient deployment of Machine Learning (ML) workloads on heterogeneous edge hardware platforms in space. Leveraging container-based virtualization (Docker) and an orchestration framework (Kubernetes), our approach abstracts hardware complexity and supports a variety of accelerators — FPGAs, TPUs, VPUs and NPUs — within a unified development and deployment environment. We integrate DevOps design principles delivering a reconfigurable stack that supports rapid ML model updates and deployment on target hardware. By treating satellites as extensible service platforms, we demonstrate how containerization and hardware abstraction streamline the onboarding of advanced ML algorithms, ranging from convolutional neural networks for image processing to neuromorphic paradigms for ultra-low-power inference. We detail how standardized APIs and modular workflows promote interoperability across multiple satellite systems and heterogeneous hardware accelerators.

      • 15
        Modeling Latency and Energy Trade-offs in Emerging Space Edge Computing Architectures
        Speaker: dorian chenet (Thales Alenia Space, Université de Rennes 1)
      • 16
        Intelligent Platform Study outcomes: End2end architecture to unlock System Autonomy

        The Intelligent System Initiative is a crosscutting initiative that aims to advance the autonomy of space-based systems in a disruptive way. The Initiative adopts a global system-of-system approach, exploiting synergies with application domains from a multitude of sectors.

    • Buses & Networks - SpaceWire & SpaceFibre: #1
      Conveners: Dr Bruce Yu (ESA), Pietro Nannipieri (University of Pisa)
      • 17
        A Generic SpaceWire Transport Layer

        The transport layer is the essential part in the open system interconnection (OSI) reference model, since it is the interface between the software-oriented layers 5-7 and hardware-oriented layers 1-3. On the one hand, it provides a general approach for data exchange with the software-oriented layers, independent of the underlying hardware. On the other hand, it is responsible for an efficient and reliable use of the underlying hardware. These characteristics make the transport layer crucial for the effective usage of a communication system, as it significantly reduces the implementation effort for the software-oriented layers.

        The lack of a transport layer is a huge disadvantage. Combining the functionality of different communication layers into single application specific protocols can lead to the coexistence of multiple, non compatible approaches, resulting in a higher implementation effort for integrating new applications. Therefore, the existence of a transport layer is fundamental for both communication software and hardware, to provide established communication concepts, which are a precondition for the use of standardized software libraries, and to integrate modern computing trends (e.g. Big Data, Data-Mining, machine learning, cyber security).

        SpaceWire does not yet define a general transport layer. This paper presents the approach of a minimalist SpaceWire transport layer, as common base for the implementation of higher level protocols. It comprises both the hardware related SpaceWire transport node and the associated software counterpart as well as the associated protocol. The transport layer implementation is one result of our longstanding SpaceWire development and is already in use in several robotic systems.

      • 19
        Towards a low-effort SpaceFibre evaluation
        Speaker: Rafael Plonka
      • 20
        Ultra-Fast, Low-Overhead SpaceFibre Communication for System-on-Chips
    • Exhibition
    • 10:20
      Coffee Break
    • ADHA (Architectures & Equipment)
      Conveners: Eleonora Mariotti (ESA), Mr Vilhelm Geijer (Beyond Gravity)
      • 21
        Modular and Scalable Electrical Architectures for Satellite Payloads using ADHA (Advanced Data Handling Architecture)
      • 22
        Avionics Unit Modularity Convergence across Spacecraft Classes using ADHA
      • 23
        Development and Reliability assesment of High Data Rate cPCI Serial Space Connectors
      • 24
        ADHA On-board Computer Module (AOBCM)
      • 25
        A3M - An ADHA-based scalable Solid-State Mass Memory
        Speaker: Christian Spindeldreier (DSI Aerospace GmbH)
    • Payload Processing Architecture
      Conveners: Mr Orion AZZIS (THALES ALENIA SPACE), Richard Jansen (ESA)
      • 26
        A Camera Payload and Processing Unit for Autonomous Satellite Deployment Verification accelerated by Soft GPU

        Engineering Minds Munich GmbH has developed a Camera Payload and Processing Unit (CPPU) for in-orbit monitoring and verification of satellite deployables. Reliable confirmation of solar panel or antenna deployment remains challenging for small satellites due to limited telemetry bandwidth and constrained power budgets.

        The CPPU provides a compact and dependable solution by integrating camera interfacing, image buffering, and actuator control into a single unit. Cameras can be placed up to 1 m from the processing board, enabling flexible positioning for optimal visibility of critical mechanisms. Built on FPGA and bare-metal software, the platform emphasizes deterministic operation, testability, and robustness in the space environment. A flight model has already been delivered and validated, demonstrating the maturity of the development.

        Current developments extend the CPPU with autonomous deployable-shape extraction, using a soft-GPU accelerated pipeline. The approach reduces image data from 8 Mbit to 1.6 kbit (a three orders-of-magnitude reduction) while retaining key geometric information in vectorized format.

      • 27
        From Zynq UltraScale+ to Versal AI Core based High Performance Processing solutions
        Speaker: Alexandre MEGE (Airbus Defence and Space)
      • 28
        Towards Integration of COTS Systems for High Performance Computing Applications in High-Reliability Space Systems
      • 29
        A reliable supervisor system utilizing an FD-SOI FPGA and MRAM for COTS-based payload data processing
      • 30
        Memory Synchronization in Multi-Processing Systems for Thermal Optimization in Satellite Payloads
    • Buses & Networks - SpaceWire & SpaceFibre: #2
      Conveners: Dr Bruce Yu (ESA), Pietro Nannipieri (University of Pisa)
      • 31
        100+ Gbps SpaceFibre on Space-Qualified FPGAs
      • 32
        Effective, Robust TCP/IP over SpaceFibre
      • 33
        SpaceFibre Radiation Testing on Versal
    • Exhibition
    • Buses & Networks - Ethernet (TSN/TTE) & CAN-Bus: #1
      Conveners: Dr Felix Siegle (ESA-ESTEC), Elisa Ballatore (SII)
    • 12:30
      Lunch
    • ADHA (Equipment) #1
      Conveners: Mr Dario Pascucci (Thales Alenia Space), David Steenari (ESA)
      • 36
        New Instrument Controller Electronics (NICE) ADHA Next Generation ICU
        Speaker: Dr Enrique García Núñez (Airbus Crisa)
      • 37
        High-Performance Reconfigurable Processing in Space: Utilizing the AMD Versal AI Core in an ADHA Co-Processing Module

        This paper presents the development of a High-Performance Reconfigurable Processing Module (HIPER-PRO) for the Advanced Data Handling Architecture (ADHA) based on the AMD Versal AI Core FPGA. Within an ADHA Co-Processing Module (CPM), the Versal AI Core device provides unprecedented computing capabilities for future space missions including dedicated hardware accelerators for AI/ML on-board processing task.

        Speaker: Julian Schneider (OHB System AG)
      • 38
        ADHA Co-Processor For On Board Artificial Intelligence
        Speaker: Mr David Gonzalez-Arjona (GMV Aerospace & Defence SAU)
        GMV_DAVIDGARJONA_ADHACoprocessor.pptx
      • 39
        ADHA-compliant Next Generation RIUs
        Speaker: Mr Jesus Ortiz Martín (Airbus Crisa)
      • 40
        SPACE!Box: On-Board Data Router for Future NTN and OBDH
        Speaker: Ertan Göklü (DSI Aerospace GmbH)
    • DPUs & Instrument Electronics
      Conveners: Mr Alberto Urbón Aguado (Telespazio for ESA), Mr Sybren de Jong (NLR)
      • 41
        Development Status of the 2nd-generation On-board Processing Unit Using COTS GPU
      • 42
        Data Processing Unit enhanced by AI
      • 43
        Serval Nano DPU – towards a mission-agnostic data processing unit
      • 44
        Context Imager: A Smart CubeSat Camera to Enable Intelligent Tasking of Onboard Instruments
    • Buses & Networks - Ethernet (TSN/TTE) & CAN-Bus: #2
      Conveners: Dr Felix Siegle (ESA-ESTEC), Elisa Ballatore (SII)
      • 45
        Time-Sensitive Networking for Space Systems: Enabling Deterministic Ethernet in Next-Generation Spaceflight
      • 46
        Revolutionizing the Space Industry: The Power of TSN and RTOS Integration
        Speaker: David Modroño Maeztu (System-on-Chip Engineering (SOC-E))
      • 47
        Data Distribution Service (DDS) over Time Sensitive Networking (TSN) for launchers
        Speaker: Carlos Domínguez (GMV)
      • 48
        Time Sensitive Networking for Space Applications: Definition and Demonstration
        Speaker: Kamil Grzymkowski (ITTI)
      • 49
        TSN development platform for aerospace: a versatile TSN tool for the streamlined configuration of aerospace missions in combination with RTEMS
        Speaker: Dr Jorge Sanchez-Garrido (Safran Electronics & Defense Spain)
        TSN_DevKit_EDHPC_2025_slides_Submission_Sept_10th.pptx
    • Exhibition
    • 15:40
      Coffee Break
    • ADHA (Equipment) #2
      Conveners: Enrico Melone (TEC-EDD), Julian Bozler (Airbus Space Systems)
      • 50
        An Avionics Ecosystem for Small- and Mid-Size Satellites Based on 3U-ADHA Units and Modules
      • 51
        Orion: Plug into to the future
        Speakers: Prem Kumar Hari Krishnan (Evoleo Technologies GmbH), Mr Rodolfo Martins (Evoleo Technologies GmbH)
      • 52
        LION DPU – ADHA 3U-based architecture for data handling module for safety operation
        Speaker: Mr Grzegorz Gajoch (KP Labs)
      • 53
        ADHA Hyper Compute Units (AHCU): Case-Study for Integration of COTS SoC Devices in ADHA form factor for scalable on-board data centre units
    • Payload Control & Processing Units
      Conveners: Jon Caudepon (OHB), Dr Maris Tali (ESA)
      • 54
        FPGA Based CCD Data Handling in Optical Space Missions Euclid PLATO SMILE and Solar C
      • 55
        CRIMSON - Close Proximity Operations Control Unit Development and Qualification
        Speaker: Mr Bruce Yu (ESTEC/European Space Agency)
      • 56
        Optical Network Controller Leveraging Heterogeneous Processing Systems
        Speaker: Mr Shohei Yamashita (NEC Space Technologies, Ltd.)
      • 57
        Hardware-Software Codesigned Calibration For Use Onboard HYPSO Satellites
        Speaker: Samuel Boyle (Norwegian University of Science and Technology)
    • Buses & Networks - Ethernet (TSN/TTE) & CAN-Bus: #3
      Conveners: Dr Felix Siegle (ESA-ESTEC), Elisa Ballatore (SII)
      • 58
        Increasing Dependability of Spacecraft Avionics Using Time-Triggered Ethernet

        Time-Triggered Ethernet enhances spacecraft avionics dependability by providing deterministic real-time communication and robust fault tolerance. Its mechanisms, including Virtual Self Checking Pair (VSCP) and Switch-Sourced-Sync (S3), improve error detection, isolation, and recovery, significantly reducing unmitigated error rates. Automated network verification tools further ensure configuration correctness and system reliability.

        Speaker: Mario Gartner (TTTech Computertechnik AG)
      • 59
        Modular Fault-Tolerant Avionics for Space Exploration
      • 60
        Design and Development of a Redundant Ethernet Switch for Small Satellites
        Speaker: Konstantin Schäfer
      • 61
        Improving CAN-bus in space by true CANopen
        Speaker: Mr Felix Körner (OHB System AG)
    • Exhibition
    • 20:00
      Surprise Social Event Elche City Center

      Elche City Center
  • Wednesday 15 October
    • ADHA (Building Blocks & Future)
      Conveners: David Gonzalez-Arjona (GMV Aerospace and Defence), Kostas Marinis (ESA)
      • 62
        An Overview of the Foreseen MBSE Approach for ADHA Units and Modules: Methodologies and Applications
      • 63
        Future On-Board Computer (OBC) Single-Board Computer Standardised ADHA Modules using UDSM (Ultra-Deep Sub-Micron) System-on-Chips
      • 64
        High-Performance, Multi-Lane, SpaceFibre Routing Switch for ADHA
      • 65
        ADHA Modules Based on Rad-Hard RC64
    • Advanced On-Board Processing I
      Conveners: Enrico Melone (TEC-EDD), Leonidas Kosmidis (Barcelona Supercomputing Center)
      • 66
        Real-Time Onboard Data Accumulation and Pre-Processing for the Photospheric Magnetic field Imager on ESA’s Vigil mission

        ESA’s Vigil mission is an operational mission planned to monitor the solar drivers of space weather conditions from the Lagrange point L5. The Photospheric Magnetic field Imager (PMI) on this mission shall provide full-disk vector magnetograms of the solar photosphere at a cadence of 30 minutes with 20-minute latency for its priority-1 data products. In addition, raw filtergrams and high-cadence line-of-sight magnetograms and Dopplergrams at a cadence up to 1 minute will be provided as supplementary data products. To meet the real-time processing requirements imposed by the telemetry volume, onboard pipelines are implemented in the processing unit hardware to produce low latency data products. In order to handle this computationally heavy task while meeting the latency requirement of the mission, the pipelines are implemented on a Field Programmable Gate Array (FPGA). This paper describes the series of steps involved in the first part of onboard data processing – from image acquisition and accumulation to polarimetric demodulation. It also discusses the parallel processing of the three pipelines in a resource-constrained FPGA in order to obtain a real-time processing environment which complies with PMI’s stringent requirements on accuracy, stability and reliability with the limited resources available on a deep space mission.

        Speaker: Deepa Muraleedharan (Max Planck Institute for Solar System Research, Technische Universität Braunschweig)
      • 67
        Optimizing Methane Detection Onboard Satellites: Speed, Accuracy, and Low-Power Solutions for Resource-Constrained Hardware
      • 68
        Towards real-time edge EO foundational models: CORSA on Hailo AI accelerator
        Speaker: Nick Witvrouwen (VITO)
        IEEE EDHPC 2025 - Towards real-time edge EO foundational models CORSA on Hailo AI accelerator - presentation.pdf
      • 69
        On board Data Processing Orchestrator
    • Exhibition
    • 10:20
      Coffee Break
    • DHS Architectures
      Convener: Mr Antoine Di Via (ESA)
      • 74
        Novel On-board Computer and Data Handling Subsystem for European ADCS for Earth Observation Application
        Speaker: Bojan Kotnik (SkyLabs d.o.o.)
      • 75
        Two Approaches to Space Data Handling: ALTIUS and EIS IOD ESA Missions – Classical vs. Hybrid Architectures with Supervision.
        EDHPC_paper_draft_250915.pdf.pdf
      • 76
        On-board Data Handling Security Reference Architecture
        Speaker: Carlos Domínguez (GMV)
      • 77
        Distributed COTS-based Data Handling: microHETSat Architecture and In-Orbit Experience
        Speaker: Mr Alessandro Avanzi (SITAEL S.p.A)
      • 78
        Development of Scalable Mission Computers and Data Recorders
        Speaker: Yuna Tsuji (Mitsubishi Electric Corporation)
        Abstract
    • Advanced On-Board Processing II
      Conveners: Alberto Valverde Carretero (ESA), Enrique García Núñez (Airbus Crisa)
      • 79
        Real-Time Data Processing for High-Energy Transient Detection Onboard THESEUS
      • 80
        CCSDS 123 Compression Applied to Interferograms: Demonstration of a High-performance On-board Data Compression Pipeline for the CAIRT Earth Explorer 11 Candidate
        Speaker: Korbinian Moser (OHB System AG)
      • 81
        A Structured Approach to AFR-1 Satellite Data Processing & Utilization Using SCULPT
      • 82
        Unibap Loom a real-time hyperspectral preprocessing pipeline for in orbit processing
        Speaker: Oskar Flordal (Unibap AB)
        EDHPC 2025 Unibap Loom A real-time  hyperspectral preprocessing pipeline for in orbit processing presentation.pdf
      • 83
        Bridging Reliability and High Performance in AI Execution with Radiation-Hardened Co-Processing
    • AI for FDIR & Autonomous Operation
      Conveners: Eleonora Mariotti (ESA), Dr Vito Fortunato (Planetek Italia)
      • 84
        Hera AI FDIR - On Board Telemetry anomaly detection using ML

        Abstract—Autonomous fault and anomaly detection is critical
        for ensuring the safety and success of space missions, addressing the limitations of ground-based analysis due to bandwidth
        constraints and operational delays. The conventional approach in
        Space Operations involves using Out-of-Limits (OOL) alarms for
        anomaly detection, which may prove insufficient in identifying
        and responding to complex anomalies or unforeseen novelties
        within the range of nominal values. [1], [2] In our previous
        work [3], we proposed a Machine Learning (ML) approach
        for on-board telemetry anomaly detection that addresses these
        limitations. We demonstrated a proof-of-concept integration of a
        TensorFlow model onto a radiation-tolerant LEON 3 processor
        and benchmarked various unsupervised and semi-supervised
        techniques with respect to their performance, memory footprint,
        and runtime. Our recent advancements focus on bridging the
        gap between a proof-of-concept solution and a nearly productionready system. Mainly, we focused on preparing a semi-automatic
        pipeline for model training and deployment, experimented with
        other types of machine learning models and created a patch
        for TensorFlow Lite for Microcontrollers (TFLM) which allows
        integration to LEON 3 processor while still following the guidelines regarding software safety. Additionally, we incorporated
        uncertainty quantification (UQ) techniques to provide a more
        reliable assessment of the black-box model’s outputs.
        Index Terms—anomaly detection, novelty detection, machine
        learning, LEON processor, TensorFlow, TFLM.

        Speaker: Lukáš Málek (Huld)
      • 85
        Advanced Satellite Avionics Health Monitoring and Failure Identification using Machine Learning
      • 86
        Enhanced Reliability and Autonomy for Satellite Operations Through AI-Driven Predictive Maintenance of Control Moment Gyroscopes
      • 87
        Deploying AI-based Spacecraft Telemetry Anomaly Detection on an Adaptive System-on-Chip Solution
        Speaker: Andrew Mccormick (Alpha Data Parallel Systems Ltd.)
    • Exhibition
    • 12:30
      Lunch
    • Poster Sessions
      • 88
        A Modular Building Block for Advanced Space Robotic Servo Control
        Speakers: Mr Gabriele Mantovani (Leonardo Space), Ms Francesca Cusimano (Leonardo Space)
      • 89
        Advanced Onboard Data Processing for the Photospheric Magnetic Field Imager in ESA’s VIGIL Mission
      • 90
        Analysis and Implementation of DVB-S2 in the UHF Band for STRATHcube Downlink Communications
        Speaker: Daniel Stebbings (University of Strathclyde)
      • 91
        ASIL2ECSS: Reusing Automotive Certification and Qualification Standards to Lower the Cost of Space Certification and Qualification for COTS Processors/SoC
      • 92
        Design decisions of the deep-space Data Handling Subsystem Basic Software within the Advanced Data and Power Management System (ADPMS)
      • 93
        Design of machine learning payloads for technology and operations development through the lens of two space missions
      • 94
        Enhancing Flight Software Development through a Model-Based Approach: A Case Study on Alsat-1B

        Developing satellite flight software (FSW) presents considerable challenges, requiring rigorous methodologies to ensure both reliability and efficiency. In this paper, we explore the application of Model-Based Development (MBD) to the periodic operations within the Attitude and Orbit Control System (AOCS) of the Alsat‑1B satellite. Our approach systematically models, simulates, and validates these functions using Unified Modeling Language (UML), Foundational UML (fUML), and Action Language for fUML (ALF). A pivotal aspect of our methodology is the use of ALF as an intermediary layer between the high-level model and the final code generation, ensuring that behavioral specifications are accurately translated into executable code. We evaluate the system’s robustness by simulating various error scenarios, including timing irregularities and state inconsistencies. The results demonstrate that our method facilitates early detection of design issues and supports a more reliable transition from model to code. This work highlights the potential of MBD to streamline FSW development for small satellites, offering valuable insights into enhanced testing and validation practices

        Speaker: Dr Youcef Bouziane (Satellites Development Center, Algerian space agency)
      • 95
        Evaluation of new NIRCA Mk-II ASIC in real camera configuration
      • 96
        Explaining raw data complexity to improve satellite onboard processing
        Speaker: Adrien DORISE (CNES)
      • 97
        Fast-SEnSeI: Lightweight Sensor-Independent Cloud Masking for On-board Multispectral Sensors
      • 98
        FPGA-Based Software Conception of Binning Operation On board Hyperspectral Imager
      • 99
        From Shelf to Space: A Practical Evaluation of Radiation Hardness of COTS NVMe SSDs
        Speaker: Mathieu Erbas
      • 100
        Instrument Control Unit (ICU) for Multi-Purpose Payloads: A Versatile and Modular Solution

        The increasing demand for commercial payloads has driven the development of innovative, high-performance control and data acquisition systems. In this context, the Instrument Control Unit (ICU) emerges as a key component for the efficient control and management of Electro-Optical payloads. Our research presents an advanced ICU architecture that leverages the computational power of the SAMRH71 processor alongside the real-time capabilities of the RTG4 FPGA. This synergy enables the management and processing of large volumes of high-speed data, a critical factor for modern high-resolution observation technologies.
        The ICU is designed for both high-performance data acquisition and exceptional modularity and flexibility. Its architecture facilitates integration into a wide variety of space payloads, allowing adaptation to different mission requirements. Key functionalities include TMTC (Telemetry and Telecommand) SpaceWire Interface and High-Speed Serial Link (HSSL) with Platform, Time Synchronization, Power Conditioning and Distribution and Thermal Control, and the management of up to two cameras via SpaceWire and Universal Asynchronous Receiver-Transmitter (UART) interfaces. Furthermore, the system can optionally incorporate a data compression module to reduce downlink bandwidth requirements when handling large datasets from multispectral, hyperspectral, and radar sensors. The unit is also engineered to drive stepper motor mechanisms for critical operations such as refocusing and shutter control, thus enhancing image quality.
        A robust power management strategy is implemented by conditioning power from an unregulated primary bus and distributing it effectively across various subsystems, ensuring stable and reliable operation under unpredictable conditions. The ICU supports comprehensive in-flight reprogramming of both firmware and application software, including updates to the FPGA firmware and subsystem firmware. This dynamic reprogrammability enables the unit to adapt to evolving mission requirements and significantly extends the payload’s operational lifespan.
        The core hardware components — the SAMRH71 Rad-Hard Microprocessor and the RTG4 radiation tolerant FPGA —complement each other in meeting the demanding requirements of spaceborne data acquisition. The SAMRH71 delivers high computational performance with low power consumption through its internal operating system (FreeRTOS), while the RTG4 provides real-time processing, and high data transfer performance (up to 5 Gbps) via its built-in serdes blocks. Moreover, thanks to the redundant interfaces toward platform and the high quality of components (at least ESCC Class 2 or equivalent), the ICU enhances the robustness of the Payload and its reliability figure.
        The ICU has been designed to meet the requirement of three different E.O. Payloads in development at Leonardo Space Business Unit: Very High Resolution (VHR), Thermal Infrared (TIR) and Hyperspectral (HYP). The VHR payload, optimized for high-resolution Earth observation, features a refocusing mechanism to enhance image quality for applications ranging from environmental analysis to precision agriculture. The TIR payload requires high thermal control performance, measurement accuracy and stability. Finally, the ICU is tailored for hyperspectral imaging, providing high data management capability from two cameras. These applications underscore the ICU’s versatility and its ability to serve multiple missions in Earth observation.

        Speaker: Alessio Fanfani (Leonardo)
      • 101
        Intelligent QoS Enhancement in Satellite Communication Through ML-Based ACM and CSI
      • 102
        New type of EGSE for ADHA modules / units
      • 103
        OBPMark and OBPMark-ML - Computational Benchmarks for On-Board Data Processing and Machine Learning in Space Applications
      • 104
        Onboard Super-Resolution Processing Using Half-Pixel Shift Imaging on FPGA SoCs
      • 105
        PrAICC: A Predictible Inter-Core Communication Model for AMP systems
        Speaker: Sébastien Levieux (Université de Bretagne Occidentale)
      • 106
        Rad-Hard Telemetry and Telecommand Mixed-Signal IC Suitable for RIU, RTU, and ICU Satellite Subsystems
        Speaker: Dr Ernesto Pun-García (ARQUIMEA Research Center)
      • 107
        The Space Power Standard: Architecture, Behavior and Connectivity
      • 108
        Towards Efficient On-Board AI: Performance Benchmarks of the Jetson Orin NX for Space Applications
        Speaker: Sebbe Van der Smissen (EDGX)
      • 109
        Verification of the Payload Data Handling & Transmission (PDHT) Chain implementing CFDP
      • 110
        YoShI: YOLO-ODARIS Ship-detection Interface – An Innovative Approach to On-board Data Analysis for Ship-detection
    • Exhibition
    • 19:00
      Cocktail Huerto del Cura

      Huerto del Cura
  • Thursday 16 October
    • OBC
      Convener: Kostas Marinis (ESA)
      • 111
        NANOhpc-obc: Scalable Multicore RISC-V based Fault-Tolerant High Performance OBC Platform for In-Orbit AI Applications
        Speaker: Bojan Kotnik (SkyLabs d.o.o.)
      • 112
        OBC-500: the New Space OBC by AIRBUS
        Speaker: Matthieu NOUARD (Airbus Defence and Space)
      • 113
        Modular platform for a Highly Reliable Space Computer
    • Advanced Processors & SoCs
      Convener: Richard Jansen (ESA)
      • 114
        GR765: A Radiation-Hardened, Fault-Tolerant Octa-Core SoC with Integrated eFPGA for Next-Generation Space Avionics
      • 115
        Microchip’s PIC64-HPSC: A Versatile Compute Platform for the Next Era of Spaceflight Systems
      • 116
        European Space-Ready N7 Design Platform
        Speaker: Mr Édouard LEPAPE (NanoXplore)
        250915 N7 platform EDHPC.pdf
    • RF OBP (NAV/IoT)
      Conveners: David Gonzalez-Arjona (GMV Aerospace and Defence), Max Ghiglione (ESA)
    • Exhibition
    • 10:20
      Coffee Break
    • S/C Platform Control Unit
      Convener: Mr Pasquale Tedesco (TELESPAZIO BELGIUM SRL)
      • 120
        Design & Qualification of a Satellite Security Unit for Lower-Class Missions
      • 121
        Avionics Centralized Unit – All-in-one solution for satellite platform
      • 122
        Design Drivers for SpaceVNX+, a Small Form Factor Electronics Unit for Space Applications
      • 123
        Vega-E methalox engine controller
        Speaker: Mr Jesus Ortiz Martín (Airbus Crisa)
    • AI Acceleration on FPGAs and HLS
      Convener: Emrah Tasdemir
      • 124
        On-orbit data processing utilizing FPGA-accelerated deep learning models
      • 125
        Enabling the Hardware Acceleration of Residual Layers within the FPG-AI Framework for Space Applications
        Speaker: Lorenzo Ciacchini (University of Pisa)
      • 126
        FPG-AI for On-Board AI Acceleration: A Case Study for Semantic Segmentation of Maritime and Terrestrial Areas
        Speaker: Tommaso Bocchi (Università di Pisa)
      • 127
        Accelerating Neural Network Inference in space by offloading heavy operations on systolic arrays
      • 128
        Efficiently Escaping Low-Level Design in Digital Microelectronics by Wise Auto-Coding of HDLs from High-Level Models
        Speaker: Mr Alberto Urbón Aguado (Telespazio for ESA)
    • RF OBP (SAR)
      Conveners: Ken O'Neill (AMD), Max Ghiglione (ESA)
    • Exhibition
    • 12:30
      Lunch
    • Mass Memory & Compression
      Conveners: Dr Felix Siegle (ESA-ESTEC), Julian Bozler (Airbus Space Systems)
      • 134
        MMU-NXT – Power and Thermal Design of a Next Generation High Data-Performance Mass Memory Unit

        The increasing data rate demands of upcomingEarth observation missions require next-generation mass memoryunits (MMUs) capable of significantly higher throughput thancurrent solutions. In response, the MMU-NXT project — devel-oped within the ESA GSTP framework — introduces a state-of-the-art memory system featuring high-performance componentssuch as a Versal FPGA, DDR4 RAM, QDRII+ SRAM, andhigh-speed SpaceFibre interfaces, supporting data rates up to20 Gbit/s and 48 Tbit storage capacity. This paper focuses onthe power architecture of the Mass Memory Module (MMM),addressing the challenges of delivering precise and efficientpower to multiple high-current and noise-sensitive voltage rails.In addition, the thermal management strategy, including heatextraction techniques for the FPGA and memory components, ispresented and validated through simulation. The results providea robust baseline for future high-performance satellite memorysystems.

        Speaker: Markus Ahrens (DSI Aerospace GmbH)
      • 135
        Challenges in the use of a Third Generation Flash Memory for space applications
      • 136
        Towards NVMe SSD in space
      • 137
        CCSDS124-Compliant Minimal-Footprint IP Core for Real-Time Telemetry-Data Compression
        Speaker: Samuel Torres-Fau (IUMA - Universidad de Las Palmas de Gran Canaria)
    • AI Acceleration with GPUs & Dedicated HW
      Convener: David Steenari (ESA)
      • 138
        Extension to Vector Operations of a Soft GPU Core for Machine Learning Acceleration in Space
        Speaker: Mr Matteo Monopoli (University of Pisa)
      • 139
        The Great Coral Reef: Modular AI/ ML Task Acceleration for Onboard Data Processing
        Speaker: Bernát-Kristóf Vescan-Bakcsy (Shobolinsky)
      • 140
        Dynamic Power Allocation for High-Performance AI Inference on GPUs in Spaceborne Applications
      • 141
        Hardware agnostic neural network embedding
      • 142
        Leveraging CUDA Middleware to Enhance Fault Tolerance of GPUs Under Radiation Exposure
    • RF OBP (COM)
      Conveners: Dr Adem Coskun (ESTEC), Mr Raúl Regada Alvarez (Thales Alenia Space)
      • 143
        Feasibility of Advanced COTS RF Transceivers for Radio Frequency Payload Processing
        Speaker: Dr Adem Coskun (ESTEC)
      • 144
        Heterogeneous Compute for Regenerative 5G-NTN Processing: A Versal-Orin Payload Design
        Speaker: Mr Wouter Benoot (EDGX)
      • 145
        Synthetic Data Generators for Enhanced Space-based Network Traffic Modeling

        Synthetic data generators (SDGs) are indispensable tools in telecommunications and satellite communications, providing a means to simulate otherwise hard-to-obtain realistic traffic scenarios for pre-deployment testing and system optimization. This paper introduces a framework for generating synthetic bandwidth demand data by integrating macro-scale and micro-scale approaches. The macro-scale SDG models long-term trends, daily and weekly seasonality, random noise, and occasional spikes over an extended period of time, typically a year. In contrast, the micro-scale SDG captures short-term, minute-level variations within a day or week, adjusted for different application demands such as phone calls, video calls, and video streams. The proposed ensemble SDG merges these scales, producing synthetic datasets that provide high fidelity in both broad and granular temporal views of bandwidth demand. We further extend the model by scaling demand with population density and projecting it onto satellite beam footprints for SatCom applications. This paper details the mathematical formulations, implementations, and theoretical underpinnings of each SDG component, demonstrating their effectiveness and realism through experimentation. The proposed framework supports a wide range of applications, enhancing the ability to plan, optimize, and innovate in the field of (not only satellite) telecommunications.

      • 146
        Prodige processors family: from 5G/6G to GNSS & PNT applications
        On-Board_Prodige_applications_CA_AC (002).pdf
        On-Board_Prodige_applications_Presentation.pdf
      • 147
        Onboard Machine Learning for Satellite Edge Computing: The SPAICE Project Use Case
    • Exhibition
    • 15:40
      Coffee Break
    • SW Execution Platforms
      Convener: Maxime Perrotin (ESA)
      • 148
        Design and application of SAVOIR File Management System Library for ICE Cube OBCU
      • 149
        CUBO: Developing a generic building-block ecosystem for on-board processing products based on NG-Ultra
      • 150
        Lua Scripting for Distributed Heterogeneous Processing On-Board Satellite Platforms
      • 151
        Telemetry and telecommand packet utilization - on the upcoming update
        Speaker: Arnaud Bourdoux (European Space Agency)
    • Performance & Computational Benchmarking
      Conveners: Aubrey Dunne (Ubotica Technologies), Dr Maris Tali (ESA)
      • 152
        Design and Implementation of an Open Source Machine Learning Benchmarking Suite for On-board Space Systems
      • 153
        On-Board Performance Benchmark (“OBPMark”) of Arm NEON SIMD on Teledyne e2v LS1046-Space and LX2160-Space Space-Grade Processors
      • 154
        High-Performance AI Inference for Agile Deployment on Space-Qualified Processors: A Performance Benchmarking Study
      • 155
        Evaluating Pseudo-Quantum Algorithms for Autonomous Spacecraft Optimization: A Comparative Study of FPGA, CPU and GPU Implementations
    • AI Engines & Neuromorphic
      Convener: Laurent Hili (ESA)
      • 156
        GRAIN – towards event-based AI in space
      • 157
        FPGA Prototype of CGR-AI Engine for Space Systems: Step Towards UDSM Implementation
        Speaker: Ms Gabriela Mystkowska (University of Pisa)
      • 158
        Ramon.Space RC64 and NuStream with Klepsydra AI: Rad-hard High Performance On-Board AI
      • 159
        Evaluation of Neuromorphic computing technologies for very low power AI/ML applications
        Speaker: Roland Brochard (Airbus Defence & Space)
        NEURAVIS_EDHPC_article_Brochard_Lebreton.pdf
    • Exhibition
    • 19:00
      Gala Dinner
  • Friday 17 October
    • Flight Software Use Cases
      Convener: Arnaud Bourdoux (European Space Agency)
      • 160
        Flight Software for Swarms
        Flight Software for swarms_EDHPC (presentation).pptx
      • 161
        The SVOM/ECLAIRs onboard software
      • 162
        Advances in Category-A Flight Software Production and their Application to I-HAB
        Speaker: Andoni Arregi (GTD GmbH)
      • 163
        NAVIGA GNSS ASW: GNSS Receiver Application Software for Launch and Re-entry Vehicles based on AGGA-4
    • AI Model Optimization & Reliability
      Convener: Gabriela Mystkowska (University of Pisa)
      • 164
        Knowledge Distillation with Pseudo-Labeling for On-Board Earth Observation AI
        Speaker: Aubrey Dunne (Ubotica Technologies)
      • 165
        Edge SpAIce: Deep Neural Network simplification pipeline for Onboard Data Reduction
        Speaker: Nimesh Tahalooa (Agenium)
      • 166
        NASEO: Neural Architecture Search for Earth Observation Onboard Processing
      • 167
        Reliability Enhancement of CNNs for Multispectral Images Segmentation on Earth Observation Microsatellites
        EDHPC2025_Argotec_ReliabilityEnhancement.pptx
    • Exhibition
    • 10:20
      Coffee Break
    • Design Methodologies, Emulators & Simulators
      Convener: Jorge Lopez Trescastro (ESA)
      • 168
        SKE: emulation of on-board computer environments in operational simulators

        SKE is a software application for general-purpose Linux host servers that allows to emulate the partitioned environment designed for computers on-board satellites running mixed-criticality systems that require time and space partitioning and fault detection and isolation. The benefits of using SKE are manyfold, from helping to develop in Linux environments the mentioned systems that will run on top of the XtratuM/NG (XNG) hypervisor, up to be exploited by operational simulators to run on-board computers faster than real time. In this latter context, this paper shows how SKE is being integrated in the CNES’s KOSMOS framework to provide the on-board computer environment inside a full numerical simulator of a swarm of satellites. SKE is aimed to provide the expected functionality of the XNG hypervisor, offering faster-than-real-time performances when executing the flight software and still keeping a good level of representativity in terms of functional behaviour.

      • 169
        An Open-Source Approach for Emulating Complex Embedded Systems: Enhancing Software Verification with Radiation-Induced Fault Injection
        Speaker: Maxim De Clercq (EDGX)
      • 170
        Hardening On-Board Software: a Low-Overhead Compiler-based Approach
        Speaker: Mr Emilio Corigliano (Politecnico di MIlano)
    • AI Development , Tools & Simulation
      Conveners: Alexandre MEGE (Airbus Defence and Space), Filomena Decuzzi
      • 171
        On-Board Data Processing and AI Facility: A Modular Hardware-in-the-Loop Testbed for Space Applications at the Edge
        Speaker: Lyana Usa
      • 172
        Composable AI Pipelines for Onboard Earth Observation Enabling Few-Shot, Hardware-Aware and Sensor-Agnostic Development via Knowledge Distillation
        Speaker: Luca Colomba (AIKO Srl)
      • 173
        Preliminary Design of the Stellar Apps Software Platform for Developing and Executing On-board Applications

        The German Aerospace Center (DLR) is developing Stellar Apps, an on-board application platform designed for space missions. Third-party applications and system services are deployed as Apps. These Apps can be executed in isolated environments with configurable access to the spacecraft and its computing resources. This allows users to regularly add, replace, remove, and update Apps to improve the flexibility and reusability of multipurpose spacecraft. Complex applications can be executed and tested in a secure environment, reducing their time to orbit. API-based communication between Apps and hardware allows the Stellar Apps platform to be used on a wide variety of spacecraft, including satellites, rovers, space stations, and entire satellite constellations. Access to commonly used artificial intelligence libraries and accelerators paves the way for future space applications. Stellar Apps provides end-to-end services ranging from development on the ground to deployment of Apps in space. The platform is currently available as a prototype at the German Aerospace Center (DLR) and is planned for an in-orbit demonstration during the second year of DLR's CAPTn-1 mission. This paper presents the preliminary design of the software platform.

        Speaker: Mr Daniel Lüdtke (German Aerospace Center (DLR))
    • Exhibition
    • 12:10
      Wrap-Up & Farewell Lunch
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