AMICSA & DSP 2016

Radiation Intelligent Memory Controller IP Core

15 Jun 2016, 18:15

1h 15m

Gothenburg, Sweden

No preference DSP Day: DSP IP cores and related IP including NoC Session 4: DSP Day Reception and Poster Session

Speakers

Mr Charles Sellier (3D PLUS)Mr Pierre-Xiao WANG (3D PLUS)

Description

I. INTRODUCTION DDR2 SDRAM is a very attractive technology for space application thanks to its high density and high speed. However, o move it into space application, it is quite complicated to handle it because of the following reasons: - Complex Behavior under radiation – No Rad Hard device available - Volatile – Data loss risk if any functional issue - Difficult to handle Micro-BGA for Space applications - Short life cycle – new device every 6 months That is the motivation to develop a RIMC IP core provided a full protection against the DDR2 radiation soft effects such as SEFI and SEU. From user point of view, all radiation protections are transparent, and the RIMC provides a standard AMBA/DFI compatible interface to targeted most space FPGAs. Figure1 shows the solution’s architecture overview. Figure 1: Overview ![RIMC2][1] II. RIMC ARCHITECTURE The RIMC is defined by 2 interfaces (see Figure 2): - The user interface, AMBA compliant. This interface contains at least one AHB bus, and may contain an optional APB bus for user dynamic configuration. These busses are compatible to AMBA 2.0 - The DDR PHY interface, compliant to DFI 2.1 (depends on different FPGAs) This interface is used to send commands and data to the DDR components through the DDR PHY. The RIMC controller can be configured by the core logic using 2 different AMBA interfaces: - Slave AHB interface with specific address mapping (1 area dedicated to DDR memory array and 1 area dedicated to internal registers) - Slave APB interface dedicated to internal registers Figure 2: RIMC Interface ![RIMC3][2] The RIMC is highly configurable to be compatible with most of user designs: - User data width (from x8 to x128) - Hamming or Reed-Solomon(RS) ECC selectable - Configurable up to 8 AHB slave interfaces - Configurable DDR2 ranks to increase memory capacity - Clock&ODT setting compatible with 3D PLUS modules - Capability to manage memory redundancy design The RIMC first version is to address FPGA development, and it is commercially available. III. MEMORY RADIATION ERRORS & IP CORE PROTECTIONS The DRAM radiation errors can be simply classified as below in 2 categories: Hard Errors and Soft Errors. The Hard Errors create irreversible errors when the threshold or limit have been passed. 3D PLUS propose a radiation tolerant DDR2 memory die with the guarantee of TID>100Krad(Si) and SEL>60Mev.cm²/mg. This paper will not present detail results on TID & SEL guarantee of the memory die. On the other hand, as semiconductor feature size scaling down, the soft errors (SEU and SEFI in case of DDR2) easily can be dominated events, especially SEFI, to DDR2 memories under radiation environment. However, each semiconductor, even each DDR2 Part Number from same semiconductor, will bring totally different SEU & SEFI results. To reach a real Rad-Hard DDR system, a well-evaluated specific DDR2 memory and its tailored controller, for example: identify memory different types of SEFI and select the correspondent mitigation strategies to guarantee no data loss, are mandatory. A. IP Core SEU Mitigation The RIMC can be configured at different types of ECC based on error rate tolerance, and here is an example of Reed-Solomon code as in figure 3 for 32b data and 50% overhead [RS(12;8), m=4, Global Bus = 48bits]. Figure 3: Example of data path with RS code, component Data Bus = 8 and DDR Data Bus = 32 ![RIMC4][3] As this RS ECC structure, The RIMC IP core(3D PLUS P/N: 3DIPMC700) can correct up to 8 bits error (row error) in one die per 48b, and 2 SEUs in the same address of different die per 48b. In case of scrubbing applied, the worst case (one particle create 2 upsets in 2 dice) in correctable error rate will be 3.8E-9 upset/day/module. Please note that 3DIPMC700 provides several different types of ECCs, and here is the error rate with Figure 3 data structure. The other ECCs (ex: Hamming) or other structures will bring other results. B. IP Core SEFI Protection Single Event Functional Interruption (SEFI) - a condition which causes a temporary non-functionality or interruption of normal operation induced by an energetic particle in the affected device, are very critical to space design. Mentioned at the beginning of this chapter, as feature size scaling down, the modern DRAM components have lower SEFI threshold and bigger cross section, which makes the SEFI easily becoming the dominated event. Moreover, unlike the SEU correctable by ECC, SEFI can easily bring system interruption or data loss and damage the whole sub-systems. Traditionally, SEFI mitigation is to power cycle or reset the component after SEFI happened, which means to restore or recover the component from a SEFI; However, power cycling will lead data loss, and in most case power lines are merged together, so not only the SEFI die data lost, but also all the dice managed by same power lines will have data loss. To avoid all these negative impacts from SEFI, a patent-pending SEFI protect technique has been designed and embedded in RIMC IP Core to prevent SEFI to replace traditional “after SEFI happened and recover” strategy. This SEFI protection is transparent to user and integrated in the RIMC IP core. Verification test had been performed at Radiation Effects Facility, University of Jyväskylä, Finland (RADEF) to confirm the protection, here below is the result: Table 1: 3D PLUS DDR2 Memory module SEFI results under RIMC Protection ![RIMC5][4] Ion LET[MeV/mg/cm2] Rang[microns] Fluence[p/cm²] Sample/Runs SEFI 20Ne+6‡ 3.63 146 >1E6 1 No 40Ar+12‡ 10.2 118 >1E6 5 No 56Fe+15 18.5 97 >1E6 5 No 82Kr+22 32.2 94 >1E6 >10 No 131Xe+35 60.0 89 >1E6 6 No No SEFI observed till LET>60Mev-cm2/mg. As a general use purpose controller IP core, RIMC is designed for any JEDEC standard DDR2 SDRAM. But please note that this patent-pending SEFI protection technique is not a universal solution, and only can be used to the die embedded in 3D PLUS DDR2 modules. On the other words, RIMC IP core can be used with any other DDR2 die, and the SEFI protection should be deactivated. IV. CONCLUSION A RIMC IP core has been proposed to reach a radiation hardened DDR2 solution. The solution includes the radiation tolerant DDR2 module with SEL immune and TID guarantee and RIMC IP core to specifically manage the SEU and SEFI of the DDR2 module to reach: TID>100Krad(Si) SEL immune > 80Mev.cm2/mg SEU immune by design (3.8E-9 upset/day/module) SEFI immune by design (LET>60Mev-cm2/mg) [1]: http://gdriv.es/rimc/rimc2.jpg [2]: http://gdriv.es/rimc/rimc3.jpg [3]: http://gdriv.es/rimc/rimc4.jpg [4]: http://gdriv.es/rimc/rimc5.jpg

Summary

Abstract— a radiation intelligent memory controller (RIMC) IP core is proposed to work with a specific DDR2 SDRAM structure to reach a Radiation Hardened (RH) DDR2 SDRAM Solution. The IP core provides protection against Single Event Upset (SEU) and Single Event Functional Interruption (SEFI), combines the TID and SEL guarantee from the memory die to reach a hardened solution. This high performance RH DDR2 solution is suitable for all space applications such as commercial or scientific geo-stationary missions, earth observation, navigation, manned space vehicles and deep space scientific exploration.

Index Terms—DDR2 Controller, Radiation Hardened, IP Core