AMICSA & DSP 2016

Europe/Amsterdam
Gothenburg, Sweden

Gothenburg, Sweden

Boris Glass (ESA) , Roland Trautner (ESA) , Sandi Habinc (Aeroflex Gaisler AB)
Description

ESA's AMICSA

6th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications
12th - 15th June 2016

Organized in collaboration with ESA, Cobham Gaisler and our Sponsors, provides an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

  • Radiation Effects on analogue and mixed-signal ICs
  • Methodologies for Radiation Hardening on analogue circuits at cell-, circuit-, and system design level
  • Radiation-hardened technologies for analogue ICs
  • Radiation tests of analogue and mixed-signal ICs
  • Qualifying and quantifying radiation-hardness of analogue circuits
  • Space Applications for analogue and mixed-Signal ICs
  • Analogue intellectual property and re-usability of analogue circuits in space
  • Needs and Requirements for analogue and mixed-signal ICs in future space missions
  • In-orbit Experiences and flight heritage of analogue and mixed-signal ICs

 

ESA's DSP Day

3rd ESA workshop on Digital Signal Processing for Space Applications
15th - 16th June 2016


Organized this year in conjunction with AMICSA, provides an overview on relevant development roadmaps, updates on Digital Signal Processing technology for space applications, and the results of contractual activities for the development of DSP rad-hard components, related equipment, IP cores, and software.

  • DSP IP cores and related IP for future SoC designs
  • Space qualified DSP components
  • COTS DSP components for space applications
  • DSP boards, software development environments, libraries and related software
  • Test, verification and qualification of DSP chips
  • Status and results of DSP related ESA contracts
  • DSP and FPGA: synergy, competition, and future integration
  • Requirements and needs for future space DSPs
AMICSA Workshop Proceedings
ESA DSP Day 2016 Round Table Discussions
ESA DSP Day 2016 Workshop Proceedings
Poster
    • 17:00 19:00
      Welcome Reception and Registration 2h
    • 08:30 09:00
      Registration 30m

      Open from 8:30 to 17:00

    • 09:00 09:40
      AMICSA: Welcome and Introduction
      Conveners: Mr Boris Glass (ESA) , Mr Sandi Habinc (Aeroflex Gaisler AB)
    • 09:40 10:40
      Space applications for analogue and mixed-signal ICs
      Convener: Mr Angelo Consoli (Saphyrion)
      • 09:40
        Rad-Hard Microcontroller For Space Applications 20m
        **Abstract** This paper describes a mixed-signal LEON3FT microcontroller ASIC (Application Specific Integrated Circuit) targeting embedded control applications with hard real-time requirements. The prototype device is currently in development at Cobham Gaisler, Sweden, and IMEC, Belgium, in the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA). The presentation and paper will describe the architecture and functionality of the device. This abstract describes an on-going development where the devices are in the specification stages before detailed implementation phase. The presentation and final paper will contain further details on the device and will describe progress made during the activity. **Background** Software based data acquisition/processing and simple control applications are widely used in many spacecraft subsystems. They allow implementing software based control architectures that provide a higher flexibility and autonomous capability versus hardware implementations. For this type of applications, where limited performances are requested to the processor, general purpose microprocessors are usually considered not compatible due to high power consumption, high pin count packages, need of external memories and peripherals. Low-end microcontrollers are considered more attractive in many applications such as: - propulsion system control - sensor bus control - robotics applications control - simple motor control - mechanism control - power control - particle detector instrumentation - radiation environment monitoring - thermal control - AOCS/GNC (Gyro, IMU, MTM) - antenna pointing control - RTU control - Simple instrument control - Wireless networking In these kind of applications the microcontroller device should have a relatively low price, a low power consumption, a limited number of pins and must integrate small amount of RAM and most of the I/O peripherals for control and data acquisition (serial I/Fs, GPIO’s, PWM, ADC etc.). The requirements for memory and program length are usually minimal, with no or very simple operating system and low software complexity. **Microcontroller Applications** Spacecraft subsystem control and monitoring of parameters such as power supply voltages, currents, pressures and temperatures are ideal applications for the LEON3FT microcontroller. Bridges between different communication standards or interface of an equipment towards a higher level controller or the central On Board Computer (OBC) are also ideal applications for the LEON3FT microcontroller. The LEON3FT microcontroller can perform advanced data handling to offload any higher level controller or the central On Board Computer (OBC). By hiding the data handling details the transmitting data volume can be reduced and simplified functionalities and timing requirements are requested to the higher level controller. The LEON3FT microcontroller integrates several on-chip data bus standards, such as SpaceWire, CAN, MIL-STD-1553, I2C, SPI, UART and can easily provide data packetization for serial communication using standard protocols. The microcontroller can also efficiently replace FPGAs in accomplishing the above functionalities. Generally the FPGA implementation is faster but much more complexity and flexibility can be captured in the software of a microcontroller even with limited processing capability. The correct use of FPGAs in space applications can be complex to achieve and also cost, package size and availability of integrated analog functions can favour the use of a microcontroller with respect to FPGA. Below are listed a number of possible microcontroller use cases and specific applications. - Nanosatellite controller - Instrument Control Unit - Remote Terminal control - Propulsion Unit control - Electric Motor Control **Processor Performance and Determinism** For applications demanding determinism on nested interrupts, a special interrupt handling scheme will be implemented in software where nested interrupts are allowed to occupy one additional register window. The number of levels of nested interrupts that can be handled without additional timing penalty depends on the complexity of the software implementation. In the architecture, deterministic interrupt latency will be achieved by: - Running software (including interrupt handlers) from local RAM and accessing any data needed during the interrupt handling through port separate from AMBA ports. - Adapting the register window usage (using a flat model) structure to avoid unexpected window over/underflow traps. This is done in the compiler and application code, and most OS code does not need modification. - The alternate window pointer feature from the SPARC V8E extension to allow window over/underflow handlers to run with traps enabled. - Register file partitioning to allow partitioning of the register file (the windows) to different “contexts”. Contexts can for example be threads to speed up context switching and/or interrupt contexts to dedicate windows to ISRs. **SPARC Reduced instruction set** LEON-REX is an extension to the SPARCv8 instruction set. Similar extensions exist for other architectures such as THUMB/THUMB2 for ARM and MIPS16 for MIPS. The reduced SPARC V8 instruction set variant has been developed by Cobham Gaisler and is integrated into the device. The main design goal has been to reduce code size, thereby reducing memory storage needed for the code, and to reduce memory bandwidth needed for the instruction code fetching. Another design goal is to allow retrofitting the extension in existing LEON3/LEON3FT pipelines and into the existing software/compiler stack, and to provide backward compatibility. User can develop C code as usual (with bare-C or a small RTOS) and the existing LEON environment (GRMON, compilers etc) can be used for development. LEON REX is designed to allow gradual transition where existing SW environment can be used unmodified and converted piece by piece to use new instruction set. The compressed instruction set is an optional extension of the SPARC V8 ISA, and existing code can be used without modification. Compressed and regular code can be mixed in the same application, thus the user can avoid changing critical code that has already been validated. The first version of the instruction set extension has been specified and tested on prototype hardware and tests has shown that a compression ration of 30-50% compared to normal SPARC V8 code is achievable in a real world scenario.
        Speakers: Mr Fredrik Johansson (Cobham Gaisler) , Mr Jan Andersson (Aeroflex Gaisler)
        Paper
        Slides
        summary
      • 10:00
        Digital Programmable Controller (DPC) : from Concepts to Space Applications 20m
        The presentation covers the key features of the Digital Programmable Controller ASIC (DPC) that have been validated during the development phase. It includes informations regarding radiations, explanations on the qualification process and associated TRLs, NEOSAT applications including analog IP and reuse of analog circuits in space, and other applications developed with partners
        Speaker: Mr Marc Fossion (Thales Alenia Space Belgium)
        notes
        Paper
        Transparents
      • 10:20
        MEMS Gyroscope Demonstration for Space Application, using a DPC 20m
        This paper reports the prototyping and performance evaluation of a vibrating structure connected to the Digital Programmable Controller (DPC) developed by Thales-Belgium (TAS-B) in a gyroscope application. ONERA has been developping vibrating MEMS inertial sensors for various applications. The VIA cell (Vibrating Beam Accelerometer family) is already in use in the french civil and defence industry. The VIG cell (Coriolis Vibrating Gyroscope family) has been proposed for space applications, in the frame of low cost assistance gyroscope associated with star trackers on satellite platforms : detumbling, slowing down satellite rotation to allow star tracker acquisition or recovery. During previous activities several aspects of the VIG have been investigated, in the objective of a future qualification. The gyroscope quartz cells endured radiations successfully up to geostationary dose, and could also withstand launcher vibrations. Shocks were also acceptable with intercalated passive absorber. Concerning electronics, the design and realization of an ASIC was initiated, but prohibitive cost prevented from further development. Nevertheless it was assessed that the electronic architecture of the ONERA gyroscope was compatible with the DPC developed by TAS-B. Electronic architecture of the gyroscope has been mapped on the DPC cores and peripherals, and requirements set in terms of A/D D/A converters, voltages, CPU usage, and communication with host. Once the chip was released recently, the opportunity to build a demonstrator was found with the french space agency. A DPC Reference Kit (DRK) is used in this project. It consists in a true qualified DPC, mounted on an evaluation board with power supplies, I/O connectors and programmer access through JTAG. The DRK comes together with software tools (compiler, debugger, configuration manager), offering the developper a complete toochain from C source code to oscilloscope view of signals. In the present work, the core functions of the gyroscope application have been developed and characterized. First a Direct Digital Synthesizer (DDS) has been implemented with a particularly high resolution of 0.001 Hz, in order to accurately drive at resonance the high quality factor vibrating cell. A pair of ADC are operated synchronously with the synthesizer to acquire the amplitude and phase of Drive and Sense signals coming out of the vibrating cell. ADC are digitally demodulated in real time (~100 kHz) using the hardware Multiplier/Accumulator of the DPC, and deliver in-phase and quadrature components to the second DPC core. Further processing is performed, such as an embedded PLL for the resonator, and a decimation filter to scale down the raw data stream to the sampling rate configured by the user, which takes place in a standard desktop computer running the demonstration OBC software. The gyroscope data frames are composed and transmitted by the third core on a serial port. All these functions perfectly match the intentional asymmetric core design of the DPC, and all three cores are in use in the application. The program memory is tiny for each core (4K, 8K, 16K), but keeping an eye on assembler generated by the compiler allows the programmer to write clean yet efficient code. The performance of several functions of the DPC have been evaluated in real conditions, such as ADC resolution. the word length of a single acquisition is 13 bits; when measuring a constant voltage, the ADC resolution is 0.1 lsb after averaging, which is equivalent to 16 bits at 10 ms, limited by 1/f noise. But when measuring a modulated signal on a carrier, the 1/f noise disappears and the resolution is 0.0005 lsb at 100 s (corner frequency is about 0.1 Hz), which is equivalent to 23 bits. Therefore we conclude on the use of the DPC for metrology applications.
        Speaker: Dr Jean Guerard (ONERA)
    • 10:40 11:10
      Coffee 30m
    • 11:10 12:30
      Space applications for analogue and mixed-signal ICs: Instrumentation
      Convener: Mr Franco Bigongiari (SITAEL S.p.A:)
      • 11:10
        SIPHRA 16-Channel Silicon Photomultiplier Readout ASIC 20m
        We present SIPHRA, an integrated circuit (IC) for the readout of single photon detectors, such as photomultiplier tubes (PMTs), silicon photomultipliers (SiPMs), and multi pixel photon counters (MPPCs). The circuit has been designed under contract from the European Space Agency (ESA) with support from the Norwegian Space Center and the University of Geneva. The ASIC requirements were derived from needs in Gamma-Ray Imaging, Polarimetry and Spectroscopy (GRIPS, [1]) and scintillating fibers for a gamma ray telescope (PANGU, [2]) and astro-particle missions (HERD, [3]). The circuit covers a wider range of technologies and applications in space and on Earth, for example, high-resolution gamma ray spectroscopy, detector front-end readout for diagnostic imaging in nuclear medicine, fast photon counting, and timing. Figure 1 ![SIPHRA ASIC block diagram.][1]: Block diagram of SIPHRA ASIC. The IC has 16 input channels and one summing channel (Figure 1): each channel can be used for pulse height spectroscopy and timing. The summing channel is important for the readout of detector arrays with monolithic scintillators. The programmable shaping time of 200 ns, 400 ns, 800 ns, or 1600 ns allows for pulse height spectroscopy with scintillators of various light decay properties. The current mode input stage (CMIS) is designed for large negative charge depending on the programmable attenuation (-16 nC, -8 nC, -4 nC, -0.4 nC) and accommodates relatively large capacitive load (several nF) and large leakage current (up to -100 μA from dark counts). Alternatively, CMIS can be by-passed to allow for positive charge depending on programmable gain (+40 pC, +4 pC, +0.4 pC). The IC contains one 12-bit analogue-to-digital converter (ADC) that allows for digitization of the pulse heights from all channels, including the summing channel at speed of 50 ksps maximum. Every channel output is available for external use and provides either the pulse height or a digital trigger/timing pulse. The programmable channel output facilitates many applications, such as, external waveform sampling and digitization, time spectroscopy, pulse counting, and triggering. The IC operates at 3.3-V supply voltage and dissipates about 15 mW without CMIS and 30 mW with CMIS. To save power, any channel or function can be programmed to power down. The ASIC has a serial peripheral interface (SPI) for programming its register settings and for relatively slow ADC data readout; faster readout up to 1Mbit/s is possible via serial data transmission line. All amplifier inputs are protected by diodes against over-voltage and electro-static discharge (ESD). The ASIC is designed in 0.35-μm CMOS process to be manufactured at a European foundry. We have manufactured test devices with the ADC, SPI, registers and buffers, and validated the design with respect to radiation. We measured a single-event-upset threshold of 50 MeVcm2/mg and we do not observe any latch-up up to the maximum tested energy of 135 MeVcm2/mg. The ASIC design validation is scheduled for the summer 2016, using a custom-made test system (Figure 2, ![Block diagram of the ASIC test system.][2]). The test system is based on the Xilinx Zync-7000 system-on-chip and IDEAS custom-made firmware for the SIPHRA ASIC readout and control. The system is controlled via Ethernet from a standard computer. The SIPHRA ASIC is located on the ROIC test board, which allows one to connect to the detector array. REFERENCES [1] J. Greiner et al., “GRIPS Gamma-Ray Imaging, Polarimetry and Spectroscopy”, arXiv:1105.1265, see also http://www.grips-mission.eu [2] Xin Wu et al., “PANGU: A High Resolution Gamma-ray Space Telescope”, arXiv:1407.0710v2, 17. Jul 2014. [3] S. Zhang et al., "The High Energy cosmic-Radiation Detection (HERD) Facility onboard China's Future Space Station", arXiv:1407.4866 , 18. Jul 2014. [1]: https://pbs.twimg.com/media/Ca8SkJ5UcAA-B9R.png:large [2]: https://pbs.twimg.com/media/Ca8TP5WUMAA7eF0.jpg:large
        Speaker: Mr Hans Berge (Ideas)
        Paper
        Slides
        summary
      • 11:30
        A New Mixed ASIC for Mars Surface Application 20m
        The Mars 2020 mission includes a rover designed to investigate key questions about the habitability of Mars, and assess natural resources and hazards in preparation for future human expeditions. The mission is part of NASA's Mars Exploration Program, a long-term effort of robotic exploration of the Red Planet. Mars Environmental Dynamics Analyzer (MEDA) is one of the Mars 2020 rover instruments being developed for the mission. MEDA will include a sensors suite to provide measurements of Mars near-surface atmosphere and ground temperatures, wind speed and direction, pressure and relative humidity. It includes also a sky pointing camera a set of photo-detectors for sky imaging and measurement of ultra-violet, visible and near-infrared irradiations at several bands allowing characterizing the atmospheric dust profile. MEDA wind sensor data acquisition will require the use of mixed-signal electronics to implement the front-end interface for the wind sensor transducers. These sensors are located around the Remote Sensing Mast (RSM) of the Rover. If the electronics is near to the transducers, and remotely connected to the rover’s Instrument Control Unit (ICU) through a simple serial link, the harness is notably reduced, saving a significant amount of mass. However, if the mixed-signal electronics is near to the transducers, it will be exposed to the Martian extreme temperatures, between -128ºC to +50ºC. The problem is not only the temperature range per se, but the fact that for a given sol, the temperature excursion can be of more than 70 to 100 degrees, so, when accumulated during all the mission (1.5 Martian years equivalent to 3 Earth years) all materials suffers from extreme wear-out and fatigue. The application (the ASIC) must be also demonstrated to withstand three times the mission life, that is, 3015 thermal cycles. This precludes the use of conventional space qualified semiconductors, which are typically down limited to -55ºC and not designed for withstanding those thermal cycles. To overcome this challenge, a mixed-signal ASIC with an operating temperature range of -128ºC to +110ºC has been developed. The ASIC need also to be packaged using specific materials and processes designed to counteract that fatigue. This was the case also of the previous ASIC developed for the REMS instrument on board Curiosity Rover. In this case, the REMS ASIC was tested to over 10.000 thermal cycles without showing any functional, electrical or mechanical degradation. The experience and heritage taken during the REMS ASIC development have been applied to the MEDA ASIC from the beginning to define the ASIC functionalities, the technologies and the verification program. The wind speed and direction are detected by the Wind Sensors using sigma-delta control loops. A wind sensor comprises four dice, each one with a temperature detector and a heater. The sigma-delta loops force the four dice to reach the same temperature, by applying the necessary power to each heater. Depending on the wind speed and direction, the loops will have to apply more power to one heater or another. Thus, by knowing each heater’s applied power is possible to calculate the wind speed and direction in one axis. This ASIC implements twelve control loops to interface with three wind sensors, one per axis. In addition to acquire the wind sensors information, the ASIC includes up to nine analog channels to interface other type of sensors, like thermocouples, thermopiles or resistance temperature detectors (RTDs). This enhances the ASIC front-end capabilities, expanding the applications range, and covering possible unexpected needs in MARS 2020 or in other missions. A digital state machine controls the wind sensor loops and analog acquisitions. It also communicates with the ICU through an UART interface, receiving configuration data for the different acquisition modes, and transmitting the wind sensors and analog acquisitions digitized data. Also, if a SEU is detected, it is reported to the ICU through this serial channel. MEDA WS FE ASIC main features: • 12 sigma-delta control loops for three wind sensors. 14-bit resolution for 0.5Hz and 1Hz acquisitions, and 13-bit resolution for 2Hz acquisitions. • 9 analog channels (switchable gain preamplifier + 15-bit ADC) with internal calibration, to acquire RTDs, thermocouples and/or thermopiles. • Digital machine to configure and control the wind sensor and the analog channels, with SEU detection. • 19200 baud UART with RS-422 interface. • Over-temperature protection for the ASIC and the wind sensors. • Internal housekeeping telemetries: Junction temperature and supply voltage. The ASIC design have been developed by the Instituto de Microelectronica de Sevilla (IMSE) and Crisa, using AMS 0.35 process and ECSS-Q-ST-60 methodology. We used rad hard by design libraries, pre-developed by IMSE, and fully characterized in temperature to -110ºC. ASIC prototypes (full functionality) will start testing in February 2016. Once validated, we will go for a second design to foundry iteration, to fine tune and improve functionalities and to package the ASICs using the final high reliability package. The ASIC will go through a full screening and lot qualification process afterwards.
        Speaker: Mr Javier Alberola-Perales (Airbus DS - Crisa)
        Paper
      • 11:50
        An Update on Medipix in Space and Future Plans 20m
        Medipix technology in the form of Timepix chips from the Medipix2 Collaboration have been in continuous operation in LEO (Low Earth Orbit) externally (in vacuum) on satellites and internally within the ISS for over three and half years. To date no failures of the Timepix chips themselves have occurred during any of the more than 30 combined exposure-years, although there have been a few minor failures in the supporting electronics. These exposures include numerous single devices powered and readout via ISS onboard laptops, self-contained battery-powered units on the first test of NASA’s new Orion MPCV during the EFT-1 flight, as well is dedicated satellite based devices including the 5-chip LUCID (Langton Ultimate Cosmic-ray Intensity Detector) device on the UK’s TechDemoSat mission. A summary of the functional information and the data gathered from these missions are presented along with the recent evaluation of n-in-p Si sensors on both Timepix and Timepix3 chips in comparison with the baseline results using the nominal p-in-n Si sensors. Future plans include flying additional single units as radiation monitors inside the ISS and the upcoming test of the inflatable Bigelow Expandable Activity Module (BEAM) module as well as deploying a multiple Timepix stack to evaluate its potential to improve incident particle ID capability. In the longer term the primary charged particle radiation monitors to be flown on the next few flights of the Orion, called the HERA (Hybrid Electronic Radiation Assessor), is undergoing the final verification process. Evaluation of the Data-Driven Timepix3 from the Medipix3 Collaboration is underway as well, and it will be used in the verification process for the frame based Timepix and Timepix2-based devices from the Medipix2 Collaboration. The Timepix2 is in the final design process at CERN, and will be evaluated for replacement in the HERA hardware for eventual operational Orion missions. The Medipix4 Collaboration has just formed and is in the process of developing the design concept for the Timepix4 chip. The University of Houston, with support from NASA and the University, is one of the founding members of the Medipix4 Collaboration, which will hopefully ultimately provide the basis for future long term radiation monitoring and active personal dosimeter devices. With Contributions from: T. Campbell-Ricketts, S. George, A. Empl, D. Turecek, L. Tlustos, A. Bahadori, N.Stoffle, R. Rios, D. Fry, E. Semones, C. Zeilin, S. Pospisil, & J. Jakubek.
        Speaker: Prof. Lawrence Pinsky (University of Houston)
        Paper
        Slides
        summary
      • 12:10
        MEDA Wind Sensor Front End ASIC 20m
        The MEDA WS FE ASIC performs two main functions. On one hand, it contains an instrumentation amplifier and a 16-bits analog to digital converter (ADC) that uses a fully differential dual-slope approach, an analog multiplexer to allow the sequential conversion of 16 analog channels, and some configurable sensor-bias circuitry. This functionality aims to measure temperatures at different points in the instrument using external platinum resistors. On the other hand, the ASIC includes a number of identical heating currents and temperature control loops used to maintain a constant temperature on external silicon dies that include platinum resistors. The heat power required by each of the dies for this purpose is measured, providing an indirect measure of the wind speed (magnitude and direction). The ASIC includes a digital finite state machine (FSM) for functions control and data communications with the external control unit. Other secondary functions include internal temperature and power supply monitoring, and authomatic heaters shut-down in the event of overheating of the external dies. A power-on reset circuit has also been included, as well as the required internal voltage and current references. The die size id 5 x 5 mm approximatelly. The specified operating (ambient) temperature range is -128 to +50 ºC, the maximum ionizing radiation dose is 9Krad, and should be latch-up free up to a LET of 75 MeV-cm2/mg. It should also be robust against SEUs and SETS up to an LET of 37 MeV-cm2/mg. The controlling FSM operated on a 2.4MHz clock, provided by the external Instrument Control Unit. The communication is based on an UART. Both the external clock and data lines (Rx and Rx) use RS-422 physical layers. The interna ADC includes its specific controlling FSM that runs on a higher 50MHz internal oscillator. The ASIC is configurable in many aspects. Configuration registers include parity check for SEUs detection. It has been packaged in a 100-pins CQFP.
        Speaker: Mr Servando Espejo (IMSE-CNM-CSIC / Universidad de Sevilla)
        notes
        Paper
        Slides
    • 12:30 14:00
      Lunch 1h 30m
    • 14:00 15:20
      Radiation-hardened technologies for analogue and mixed-signal ICs
      Convener: Mr Rok Dittrich (ESA)
      • 14:00
        Using a Standard Commercial Process for Full Custom Rad Hard Mixed-Signal Design 20m
        Mixed-signal design allows integration of further external discrete components and hence continues the dividend of integration. However, implementation of a mixed-signal flow into an operating digital or analog design flow is not a straight forward task. In space applications in addition, radiation is always an issue and ways need to be found to mitigate its effect on the circuit. Libraries using modified specialized layouts exist to create rad hard designs for digital and analog functions. Companies offer complete flows from design using pre-designed building blocks to qualified devices using proprietary libraries. Indeed, these solutions can be very efficient and minimize the risk as used library components might be working in several other designs. However, if application constraints the design to other requirements than implemented within the library cells, full custom solutions might be required to obtain the full benefit of mixed-signal. In addition to the limited availability of analog library cells for space application at the beginning of design, this has been one of the main reasons for the necessity of full custom design in our applications. Before going mixed-signal, our design flow has been focused on digital designs only and several digital ASICs and FPGAs have been successfully created. One of the main requirements was that the new analog functionality should integrate into the digital flow while preserving it. In addition, our mixed-signal designs usually have a huge amount of digital cells integrated. Consequently, the decision has been to work with a digital-on-top flow. The main design reference is a VHDL-netlist and the final layout is done using a place-and-route tool and not the full custom analog layout tool. This way, the timing information between digital sub-cells like IO-cells, a possible digital core and memory macros is in control of the digital tools and not a full custom designer only. SDF-based verification on top-level remains possible. Furthermore, the exact shape of the digital core can be adjusted easily to fit into the remaining area after placement of the analog macros. Long parallel digital interconnection buses do not have to be drawn manually with a large effort, but are drawn by the place-and-route tool. In addition, this way of designing structure offers to work with analog IPs on the long therm. As a matter of principle, the operation of implementing a memory macro can be similar to the implementation of an ADC for instance. It is instantiated within the digital netlist as a black box, with possible interface description and no dedicated analog tool chain would be required anymore. The next question is how to obtain a qualifiable rad hard design. Here the approach has been to work with an available commercial process which is tolerant enough for TID and do mitigation for SEE on system and design level rather than modifying the process or its devices. Furthermore, no dedicated rad hard digital standard cell lib should be designed and radiation tolerance should be given at netlist level. This way flexibility to adapt to other processes is retained in principle. However, not all insufficiencies of the process can be taken care of at system or netlist level. This is why radiation behavior of the process needs to be observed during process choice. Individually checked devices have been whitelisted concerning total dose and SEE behavior. Our result has been, that we can work with our technology applying the netlist mitigation techniques on digital cells. Further devices or macros which might be required, have to be observed, in addition. 3.3 Volts transistors could be used basically without any total dose concerns. Drifts will occur at higher voltage devices. Consequently, they should be avoided where possible and should not be used in analog macros where the exact parameters are important. On device level, no latch-up issues arose during single event testing. Mitigation techniques for single event effects without dedicated layout are possible. On the digital side we work with triple mode redundancy of memory and logic elements which keeps the devices clean from single events up to a certain threshold. However, as IO-cells might be a bottleneck in this case, we had to develop an own redundant IO cell to keep the complete path redundant. Digital memory macros implemented as IP cannot be implemented with triple mode redundancy on a low level, as they are fixed. Consequently, they need to be implemented redundant as block and ways to maintain the data have to be applied. This can be a continuous read and write of all memory cells in a certain time. If the data is generated periodically, it needs to be assured, that the time frame is small enough to downsize the probability of an upset. If latch-ups in IPs like memory macros occur, there are several different methods of treatment. If destructive latch-up occurs during normal operation, the macro cannot be used in normal operation. However, it still might be used for a very short time during start-up for instance as latch-up probability of the system would hardly be affected this way. During normal operation, the macro would need to be disconnected from power. If non-destructive latch-ups occur, it might be possible to power-down one instance of a redundant memory after latch-up detection. For analog cells, treating SEEs is less straight forward. As we are doing full custom design, we do not know the SEE behavior of the circuits before. We used several approaches in this case. One is to inject charge onto all nodes of few critical circuits during simulations, which is very extensive indeed. Furthermore we work with large time constants at the outputs of DACs for instance. Measured values from ADCs on the other hand are read several times to exclude incorrect measurements. Allowed signal errors due to single events are included inside our specification and the systems themselves are tolerant against short incorrect analog signals. Laser tests are used to get an idea of SEE behavior in early prototyping stages. With these approaches, we will get rad hard full-custom mixed-signal designs on a commercial process. Next step will be qualification.
        Speaker: Mr Volker Lück (Tesat Spacecom)
        CV
        Paper
        Slides
      • 14:20
        Radiation-Hardened SiGe BiCMOS Technologies for Analogue and Mixed-Signal ICs 20m
        IHP has been actively involved since many years in developing and providing un-restricted access to Process Design Kits (PDKs) for their high-performance 0.25µm and 0.13µm SiGe BiCMOS Technologies and professional services like Multi-Project-Wafer (MPW) and Low Volume (LV) manufacturing. In response to the strategic European Non-Dependence process for Critical Space Technologies for Electrical, Electronic and Electromechanical (EEE) components, aiming to ensuring European free, un-restricted access to any required space technology supply chain, IHP has been involved in the development of RadHard SiGe Process Design Kits (PDKs). For the 250nm node, a RadHard PDK SGB25RH has been developed and evaluated in accordance to the ESCC-2269010 Basic Specification “Evaluation Test Programme for MMICs” and will be requesting EPPL Listing in 2016 while for the 130nm Technology node, PDK SG13RH is under development and sensitivity to radiation (TID, DD, SEEs) is being evaluated before going through the full ESCC-2269010 Evaluation Test Programme (2017-2019) and requesting EPPL for SG13RH within 2020. The integration of Silicon-Germanium (SiGe) onto BiCMOS technology platforms have been proven an economically viable and valuable technology for the design and implementation of low power highly integrated microwave monolithic integrated circuits (MMICs) operating at very high frequencies (up to THz) together with complex CMOS functions unavailable in other technologies. SiGe HBTs exhibit intrinsic advantages – such as a very high tolerance to Total Ionizing Dose (TID) greater than Mrad(Si) and improved performances down to cryogenic temperatures – which make them excellent candidates for use in harsh environments like for space-based applications which any independent fabless Design House can use to develop electronic components like Application Specific Integrate Circuits (ASICs) or Monolithic Microwave Integrate Circuits (MMICs) for the space market ranging. TID and ELDRS Pre- and post-irradiation forward Gummel plots for an HBT arrays in SGB25RH and in SG13RH together with their Forward current gain versus total ionizing dose will be presented. It will be shown that there is some dependancy of the Base-current and Forward Beta with respect to TID up to 500krad(Si)for SGB25RH while for SG13RH there is substantially no variation. Transfer characteristics of the Standard and Enclosed Layout NMOS Transistor devices in saturation before and after TID irradiation available in SB25RH and SG13RH PDKs will be presented exhibiting very stable characteristics over 500krad(Si). Acheived SEU LET thresholds and Cross-Sections under Heavy-Ion (HI) on 1024-bit Shift Registers based on different Flip-Flops (TMR, DICE, etc..) and recommendations for use of the combinational logic elements will be presented. The content of the RadHard PDKs (devices and libraries) for 250nm and 130nm IHP SiGe BiCMOS Processes, the Test Vehicles (TCV, DECs and RIC) used in the Evaluation Tests in accordance with ESCC-2269010 and the most updated results concerning radiation tests and reliability evaluations on both CMOS and SiGe HBT devices as well as focusing on the failure modes and the required derating factors of such devices necessary to achieve reliability and mission lifetimes are presented. The presentation will conclude with a short overview of the current on-going research areas and activities and IHP’s vision to the “More-than-Moore” approach like integration of THz Devices, Embedded RF-MEMS, Heterogeneous Integration (Micro-Fluidics, Through Silicon Vias, III-V on Si BiCMOS), Resistive-RAMs and Silicon Photonics which could prove useful for future compact low weight electronic components and System-on-Chip solutions for future Space or Ground-segment applications.
        Speaker: Mr Maurizio Cirillo (IHP GmbH)
        Paper
        Slides
        summary
      • 14:40
        Incorporating more in-depth radiation knowledge in the DARE180U analog design kit 20m
        DARE180U is a radiation hardened system-on-a-chip (SoC) design platform including mixed-signal and full-custom analogue circuits. It is built on the commercial UMC L180 MM/RF 1.8V/3.3V, Single Poly 6 Metal (1P6M), P-Sub/Twin-Well CMOS technology. In order to facilitate full custom radiation aware analogue design an analog design kit (ADK) is provided. From the start this ADK targeted total-ionizing-dose (TID) requirements up to 1 Mrad. The ADK provided enclosed layout transistor support (ELT) with W/L design documentation, Cadence virtuoso pcells and an adapted layout-versus-schematic (LVS) check. Based on literature the effect of the ELT shape on the device performance can be taken into account during design phase and, by using the pcell, the layout phase can be sped up. Additionally an optional verification check is provided for well and substrate density to mitigate single-event latch-up (SEL). Over the years radiation measurement results on TID, SEU, SET and SEL have been gathered. This included measurements on test vehicles using specifically designed test structures including single devices and digital or analog building blocks, but also data from radiation tests on SoC prototypes. For the design of the test vehicles always a trade-off has to be made between budget for test structure design and (radiation) measurement and the extra gained knowledge. The results of the measurement campaign are not always fully conforming to the expectation and in that case the data post-processing has to be adapted to still derive as much information usable by an analog radiation aware designer. The provided ADK is developed to fulfill several needs of the analog designer. First of all it should be a natural extension of the provided foundry PDK and should reuse the knowledge already in there and not reinvent the wheel. The ADK should also fit perfectly in the design environment already used by the customer and be adaptable to the customer’s internal flow. Recent versions of the Cadence Spectre device simulator help the designer by giving warnings for suspicious circuits and models. To avoid warning blindness the ADK should avoid introducing warnings itself. As radiation hardness requirements are dependent on the targeted radiation environment of the final chip, the ADK should help in optimizing for this but at same time prevent the situation for worst-case overdesign as much as possible. Based on the available measurements and the given requirements the ADK has been extended with: - Fine-tuning the modeling of the effect of the shape of the ELT on the drive strength of the device. - Improved asymmetric parasitic modeling of the ELTs in the Spectre models as normal BSIM and other models assume straight devices and thus an equal length for the gate to the source and to the drain overlap. - Additional TID process corners in the Spectre models so design can be optimized for different radiation environments - Custom Virtuoso schematic checks to indicate to the designer the presence of radiation sensitive devices during the design phase (e.g. already before layout) - More extensive support of Virtuoso Layout XL features by the pcell In the paper these extensions will be discussed more in-depth together with the measurement data on which these extensions were based.
        Speaker: Mr Staf Verhaegen (imec)
        Paper
        summary
      • 15:00
        Development of a Digital Temperature Transducer ASIC in a 28 nm FD-SOI CMOS Process for a Spaceborne Low Power Sensor Bus 20m
        A geostationary satellite typically employs as many as 1000 resistive temperature sensors for its housekeeping activities. These sensors are point-to-point wired to an acquisition unit, which is often a single central interrogator system. This poses a need to develop solutions that can reduce harness complexity and weight while maintaining high reliability and keeping low cost and power consumption of the solution in mind. Digital temperature sensors fabricated as integrated circuits have become a popular choice for use in thermal management systems. The temperature sensor and the digital interface circuitry for bus-type interfaces are integrated on a single chip; thus, enabling modularity and simplicity in the system design. Implementing a sensor network in which the point-to-point connected resistive sensors are replaced with serially connected digital temperature sensors can result in a significant reduction in the amount of wiring. The selection of a suitable technology for designing such sensors is very crucial. The 28 nm Fully-Depleted Silicon on Insulator (FD-SOI) CMOS technology offers many high performance features, namely, faster switching, poly biasing, back-gate biasing for power regulation, and expected latch-up immunity. Additionally, the expected high radiation tolerance of this technology makes it suitable for the development of circuits for space applications. In this paper, we discuss the system-level requirements of a low-power digital temperature transducer application specific integrated circuit (ASIC), currently under development, in the 28 nm FD-SOI CMOS technology from STMicroelectronics. We also present our ongoing work on the chip design. The ASIC will become a part of a low power sensor bus system, to be incorporated in future geostationary satellites, where all the serially connected transducer ICs will communicate with a central interrogator module in a hybrid bus topology. The targeted temperature range of measurement is from -40ᵒC to +125ᵒC with an effective resolution of 0.1ᵒC. A measurement inaccuracy of ±0.5ᵒC is specified for the entire temperature range. On the system-level the ASIC consists of three major design blocks- a band-gap reference based temperature sensor, a sigma-delta analog-to-digital converter (ADC), and a digital serial communication interface. Additionally, circuitries for generation of the internal bias currents and low power digital calibration are included. The sigma-delta ADC has a resolution specification of 14 effective number of bits (ENOB). It is being developed in the scope of the European project called "Thin but Great Silicon to Design Objects" (THINGS2DO). Most of the analog and mixed signal blocks are powered by a 1.0 V nominal supply. For digital input/output (IO) signals a supply voltage between 1.5 V and 1.8 V is required for the IO ring. Different system-level and circuit-level techniques will be exploited to achieve low power operation of the ASIC. Design-level mitigation strategies for non-destructive single event effects (SEE) such as triplicated combinatorial logic and triplicated registers will also be employed. In line with the development of this temperature transducer ASIC, a 1st order sigma-delta modulator and its constituent operational transconductance amplifier (OTA) have been integrated as test structures on an integrated circuit (IC) called "AMBER1". The IC is realized to explore the low power features of the 28 nm FD-SOI technology. It was taped-out in November 2015 and its silicon validation is planned for the mid of 2016.
        Speakers: Mr Markus Roner (OHB System AG, Munich, Germany) , Mr Pragoti Pran Bora (Fraunhofer EMFT, Munich, Germany)
        Corrected_Abstract
        Paper
        Presenter CV
        Slides
    • 15:20 15:50
      Coffee 30m
    • 15:50 16:50
      Space applications for analogue and mixed-signal ICs: Radio Frequency
      Convener: Hans-Dieter Herrmann (DLR)
      • 15:50
        Development of a Satellite TV receiver for fibre optic distribution system 20m
        In this paper we highlight the design work performed by Riverbeck Ltd on the Romeo and Juliet chipset paid for by Global Invacom and the European Space Agency. Romeo and Juliet are application specific integrated circuits developed as the receiver element of a satellite TV, terrestrial TV and FM radio fibre distribution system. Fibre distribution of media signals is particularly attractive to multi-dwelling units where any TV or radio channel can be demanded by any dwelling. This demands the entire signal bandwidth be provided to all dwellings. A fibre system reduces the infrastructure cabling, is immune to electrical interference, suffers from less signal loss and can be passive split without detriment to reception. The fibre distribution transmitter (not within scope of this paper) frequency shift and modulates terrestrial radio, TV, and satellite signal using a 1310 nm semiconductor laser. Romeo and Juliet amplify the received photodiode signal, filter and frequency shift the 5GHz bandwidth to provide a set top box with the same data were it directly connected to a LNB. Romeo is a dual gain, low noise amplifier with differential outputs. Juliet provides broadband programmable RF gain, wideband continuous time filters to clean up the output spectrum, RF power detectors, 75Ω and 50Ω line driver outputs, phase locked loops to frequency shift the received spectrum, monitoring circuits and digital interfaces.
        Speaker: Mr Graham Leach (Riverbeck)
        Paper
        Slides
      • 16:10
        New rad-hard chip-set for radiometers 20m
        Saphyrion Sagl is developing under an ESA contract a new chip-set for L-band radiometer applications, which consists of an RF down-converter and a latched comparator (1-bit AD-converter). The chip-set is being developed in collaboration with MIER Comunicaciones, who will use it on their next generation of radiometers. At present fully operating ASIC prototypes are available and are being characterized. The RF ASIC is a single conversion superheterodyne receiver, which contains a programmable gain LNA (2 different gains), a double-balanced active RF mixer with active input signal coupler, an IF-strip comprising digitally programmable gain stages (PGAs) and a VCA stage, and an IF output buffer with power measurement amplifier. The RF chip will be encapsulated in a ceramic-metal 36 pin QFN package. The companion AD-converter ASIC - called DADC - is a 130MHz dual-channel latched comparator with direct and multiplexed outputs. It will be encapsulated in a 16 pin QFN package, also of ceramic-metal design. The new chip-set is designed to be radiation tolerant, making use of the design techniques that Saphyrion developed for its GNSS front-end chip-set consisting of SY1007 (RF down-converter) and SY1017C (ADC/DAC and interface ASIC). In this presentation the architecture of the new chip-set and the radiometer including it, as well as the design choices and trade-offs, will be presented, followed with some circuit details. Results from the electrical characterization will be presented next. As a conclusion the remaining steps towards industrialization and space qualification to ESCC9000 of the chip-set will be shown, together with the planned road-map.
        Speaker: Dr Francesco Piazza (Saphyrion)
        Paper
        Slides
        summary
      • 16:30
        25-Gb/s/Channel VCSEL Driver and Transimpedance Amplifier Array ICs in 0.25-μm SiGe:C BiCMOS Technology for Space Applications 20m
        We present monolithic VCSEL driver and transimpedance amplifier array ICs for multi-channel optical transceivers. Each IC has 3 channels and is targeted to operate at the highest data rate of 25 Gb/s/channel. Two generations of the ICs have been implemented with IHP’s 0.25-μm SiGe:C BiCMOS technology. The Gen-1 ICs contain only analog control circuits in order to focus on verification of high-speed signal path. The Gen-2 ICs are equipped with full digital control circuits with serial interface. Radiation-hardness of the digital part is achieved by adapting triple modular redundancy structures. These ICs have been developed within a European project “Multi-Gigabit, Scalable & Energy Efficient On-Board Digital Processors Employing Multi-Core, Vertical, Embedded Opto-Electronic Engines.”
        Speaker: Dr Minsu Ko (IHP GmbH, Frankfurt (Oder), Germany)
        notes
        Paper
        Slides
    • 17:30 19:00
      Mayor Reception

      A complimentary reception hosted by the Mayor of Göteborg will be held at the Dickson Palace. After a welcome by the Mayor, attendees and their companions will enjoy light snacks and a drink.

      • 17:30
        Meet in hotel lobby for 20 minute walk to the event 30m Hotel Lobby

        Hotel Lobby

      • 18:00
        Reception 1h Dickson Palace (Gothenburg, Sweden)

        Dickson Palace

        Gothenburg, Sweden

    • 08:30 09:00
      Registration 30m

      Open from 8:30 to 17:00

    • 09:00 09:20
      Keynote Speech
      • 09:00
        65nm technology developments for electronics in the LHC at CERN 20m
        The High Energy Physics experiments at CERN are preparing their detector upgrades for the period 2023-2025. Because of the increase of the luminosity by a factor around 7 coupled to large instantaneous events multiplicity, the most internal detectors (trackers) will have to be replaced, whereas for other detectors (calorimeters, muon detectors) the electronics should be exchanged to accommodate new data rates. The data volume increase is shared between defining higher detector segmentations (more readout channels) and higher rates per readout channel. The 65nm commercial technologies have been identified as the possible technology node for the development of the new readout ASICS for these experiments upgrades. The very high density offered by these technologies is beneficial for the design of the future pixel detectors, that require on-chip complex data processing across very small size pixels (50umx50um range). The characteristics of transistors are enough to reach 10 to 12 Gb/s data rates on the optical links to transmit data from the detectors to the external data acquisition systems. Various evaluations related to radiation effects have been made on the candidate 65nm technology, including very high total ionising dose up to several hundred of Mrads. Degradations effect have been observed that affect mainly the PMOS transistor at relatively high ionising dose. Complex dependencies to dose rate and temperature annealing are currently analysed. Based on transistor measurements, new parameters for both the P and NMOS transistor behaviours at 200Mrads and 500Mrads have been introduced. They are fitted to the W and L size, and actually used to predict the transistor geometries for new digital standard cell libraries. At the same time the evaluation of basic analogue circuits has started under the framework of the RD53 collaboration at CERN, that aims for the definition of advanced pixel detectors and readout systems. Test circuits that include bandgap references, I/O cells, various analogue circuits have been developed and some of them tested to radiations. More complex circuits, targeted to pixel detector readout, are also in preparation within the RD53 collaboration, that groups institutions and universities from the High Energy Physics community. An overview of the current organisation of the effort to assess the 65nm technology for the upgrade of the LHC detectors will be presented, as well as the model of organisation that has been defined to access to the foundry and to the advanced CAE tools for multi-million transistors mixed-signal ASIC designs in 65nm technology.
        Speaker: Francis ANGHINOLFI (CERN)
        notes
        Slides
    • 09:20 10:20
      Full custom digital, analogue, or mixed-signal: Data Converters (1/2)
      Convener: Dr Rajan Bedi (Spacechips Ltd)
      • 09:20
        ESA Cosmic Vision MF ASIC and IPs Development 20m
        In the radiation environment envisaged for the interplanetary mission to Jupiter named Juice, the electronic equipment will require to withstand up to 300krad of Total Ionization Dose. The availability of high performance components that can cope with that requirement is low or non-existent and for that reason ESA funded an activity to create radiation tolerant high-performance mixed-signal IPs. In the frame of the project two different ASICs where implemented: A rad-hard programmable ∑∆ modulator (CVB-001) which contains four separate ∑∆ modulator and a Rad-hard analogue front-end chip (CVC-001) which contains a Bessel Filter, a Digital to Analogue Converter, a Low Noise Amplifier and a Power amplifier. Simulation and validation results of those chips and in particular the detailed behavior of each of the IPs will be presented.
        Speaker: Mr Daniel Gonzalez (Arquimea Ingenieria S.L.U)
        Paper
        Short CV
        Slides
      • 09:40
        First S-Band capable dual 12bit 1.5GSPS ADC in flip-chip hermetic technology 20m
        In partnership with CNES, a new ADC has been developped to meet the high dynamic range as well as channel integration requirements of telecommunications payloads. It is a dual channel single core 12bit 1.5GSPS designed by e2v on ST Microelectronics BiCMOS9 technology which features 0.13µm CMOS and SiGeC NPN HBT bipolar technology (Ft/Fmax = 166/175GHz). The device is built in a hermetic flip-chip package using Aluminum Nitride material in order to reach optimized thermal performance and higher pin density. A new European Flip-Chip assembly line is being used for this device. The paper will develop the following aspects : - Target noise power ratio performance in multiple Nyquist zone. - Cross talk isolation in excess of 80dB at 2GHz. - Chosen ADC architecture. - Introduction of chained ADC synchronisation for antenna arrays (patent pending). - System benefits of S-Band high dynamic range digitization. - Mitigation of radiation effects on ST Micro BiCMOS9 technology. - Choice of package technology. - Challenges of Flip-Chip assembly at space level.
        Speaker: Mr Eric Savasta (e2v)
        Paper
        summary
        Transparents
      • 10:00
        High Resolution Radiation Hardened DAC in CMOS - SOI Featuring a Return - To - Zero Matrix 20m
        We present a current-steering, low-noise, radiation hardened Digital-to-Analog converter, optimized to operate in the frequency range between DC and 50kHz. The DAC receives 24-bit sampled data in a synchronous serial format and converts it into a differential current analog signal. It uses a third-order multi-bit Sigma-Delta modulator, which provides superior noise and linearity performance. The embedded interpolator follows a multiple-stage architecture and consists of an FIR equiripple low-pass filter followed by two cascaded stages of Half-band equiripple filters. The last stage is a programmable SINC filter, which provides variable interpolation ratios allowing sampling rates as high as 310kHz. The system operates on a single clock domain, which is provided externally. The output current matrix features a Return-to- Zero (RTZ) technique to improve the linearity by ensuring that each elementary current source is zeroed, regardless the data value of the sample sequence. The DAC is implemented in a rad-hard 150nm CMOS-SOI process, exhibits an SNR figure of better than 108dB, and consumes 62mW of power.
        Speaker: Dr Constantin Papadas (ISD)
        Paper
        Slides
        summary
    • 10:20 10:50
      Coffee 30m
    • 10:50 11:30
      Full custom digital, analogue, or mixed-signal: Data Converters (2/2)
      Convener: Mr Volker Lück (Tesat Spacecom)
      • 10:50
        Serial I/O ADCs/DACs : The Next Giant Leap in Mixed-Signal for Space. 20m
        Today, the cost and effort to develop satellite payloads has to be repeated for almost every new mission, introducing unnecessary re-design, re-test, performance, re-qualification, schedule and budget risks to key programs. Operators are constantly complaining to OEMs that the cost to develop satellites is prohibitively expensive, delivery takes too long and never right-first-time, while satellite manufacturers are handicapped by the limitations of current space electronics. Digital telecommunication payloads have become handicapped by traditional mixed-signal convertor technology: high I/O counts, large packages introducing parasitics which limit performance, complex layout and routing constraints adding to design effort and resulting in more expensive PCB fabrication, as well as the power requirements of ADCs/DACs. The current approach of developing flexible, space electronics is simply too bespoke, too expensive, too inflexible and too power consuming to deliver tomorrow's, space-enabled world for everyone. For example, the Alphasat telecommunication payload, the Sentinel Earth-observation satellite and the NovaSAR mission used 10, 8 and 12-bit ADCs respectively from the same supplier. In terms of on-board processing, the overall function of each transponder was similar, however, because each of the three missions had individual systems requirements, the mixed-signal technology that was available then necessitated the development of three, unique, avionic sub-systems triplicating effort and cost. The Alphasat and recently announced Inmarsat 6 telecommunication payloads both use ADCs from the same supplier, however, the latter uses 90 nm ASIC technology while the former uses 0.18 µm. In terms of on-board processing, the overall function of each channelizing transponder is identical, however, because both missions have individual systems requirements, two unique avionic sub-systems have had to be developed doubling effort and cost. For the first time, JESD204B, serial-I/O ADCs and DACs offer manufacturers of satellite sub-systems the possibility to continually deliver bespoke and improved levels of performance to telecommunication operators without having to re-engineer the avionics hardware. Non-recurring, design effort and costs will significantly reduce while recurring manufacturing and test costs will also decrease, allowing future satellites to be delivered right-first-time, within budget and to schedule. This innovation represents a profound advance in payload design and a hugely enabling and disruptive step-change for the satellite industry! Regardless of the SNR performance (resolution) required by individual operators, the digital interface will always remain the same thus avoiding the need to re-design and re-qualify hardware sub-systems. Only the FPGA configuration will need to be updated to reflect larger word lengths allowing future satellites to be delivered right-first-time, within budget and to schedule. To promote the new architectural concept, the paper will also propose device-level pin-outs to ensure a scalable roadmap which will allow operators to avail of bespoke and increasing performance without the need for OEMs to continually re-engineer the avionics hardware.
        Speaker: Dr Rajan Bedi (Spacechips Ltd.)
        Paper
        Slides
        summary
      • 11:10
        Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADC in Space 20m
        Feitao Qi , Tao Liu , Hainan Liu , Chuanbin Zeng , Bo Li , Jiantou Gao , Gang Zhang , Fazhan Zhao , Jiajun Luo* , Zhengsheng Han , and Zhongli Liu Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences, Beijing 100029, CHINA * Corresponding Author's Email: luojj@ime.ac.cn In the harsh space environment, analog and mix-signal circuits would suffer drastic performance degradation due to radiation effects. A monolithic, high reliability pipelined analog-to-digital converter (ADC) with 10 bits resolution and 25MHz conversion rates is presented as a prototype exhibiting benefits from RHBP and RHBD approaches. The ADC prototypes are manufactured respectively by commercial 5V 0.35um bulk and rad-hard silicon-on-insulator (SOI) technologies. And both ADCs are tested in the same conditions for comparison. The block diagram of the ADC prototype is illustrated as figure 1. ![Block diagram of the ADC prototype][1] The micrographs of ADC in different technologies are shown in Figure 2, respectively. ![Micrographs of ADC in different technologies][2] The rad-hard SOI CMOS technology adds silicon dioxide as a buried insulator layer upon silicon substrate as figure3. It provides CMOS a complete isolation between n-well and p-well, leading to the elimination of circuit latchup events. The technology is optimized and hardened to obtain excellent mitigation ability to radiation effects. ![Cross-section views of SOI and bulk CMOS technologies][3] The bulk CMOS ADC is implemented with reasonable and rigorous layout rules, resulting in the immunity of SEL and SEFI up to 63 MeV•cm2/mg linear energy transfer (LET) during SEE experiment. In order to improve the performance of anti-radiation, a suitable ADC structure is determined and designed; the current amplitude and capacitance value around certain sensitive parts are increased with special purposes. By implementing the above approaches and taking advantage of the inherent rad-hard SOI technology, the SOI-based ADC is capable of exhibiting much smaller deviations when radiated. Because most deviations could be corrected by ADC’s error correction logic with designed system redundancy, the SOI-based ADC acquires excellent rad-hard accomplishments. In contrast the bulk CMOS ADC with same schematic structure implementation could not be so efficient in experiments. The regulated performance characteristic experiment indicates that both SOI ADC and bulk CMOS ADC could achieve effective number of bits (ENOB) of 9.5 bits, spurious-noise-free dynamic range (SFDR) of 72dB, differential non-linearity (DNL) of 0.4 LSB, and integral non-linearity (INL) of 0.5 LSB. The detail performance characteristics are listed in Table 1. ![Regulated performance characteristics of SOI-based ADC and bulk CMOS ADC][4] The spectrums of SOI and bulk CMOS ADC are exhibited in figure 5. ![Spectrums of SOI and bulk CMOS ADC with a sampling speed of 25 MHz][5] The total ionizing dose (TID) experiment reveals that SOI-based ADC achieves better TID tolerance, 300krad(Si), which nearly ten times higher than bulk ADC. The comparison of their TID responses is exhibited in figure 6. ![Comparison of TID responses between SOI and bulk CMOS ADC][6] In the single event effect (SEE) experiment, both ADCs show immunities of single event latchup (SEL) and single event functional interrupt (SEFI) up to 63 MeV•cm2/mg LET. When LET is 17MeV•cm2/mg, the SOI-based ADC has a single event upset (SEU) cross-section of 3.1X10-6cm2/device, when LET is 63MeV•cm2/mg, the SOI-based ADC has a SEU cross-section of 9.6X10-6cm2/device, both lower than bulk ADC by two orders of magnitude. Figure 7 illustrates the differences of SEU cross-section between SOI and bulk CMOS ADC. ![Comparison of SEU cross-section between SOI and bulk CMOS ADC][7] In conclusion, by taking advantage of rad-hard SOI technology along with RHBD approaches, the SOI-based ADC in space exhibits better performance with respect of SEE and TID over the one using commercial bulk CMOS technology. [1]: http://img0.ph.126.net/VWFmLMmxyqPsmKYmCE2qmg==/6598074720343985115.jpg [2]: http://img2.ph.126.net/RmwEafhqOBsTYn4u6UyxEw==/6598219855878851729.jpg [3]: http://img1.ph.126.net/zg7jwdbTwOQOt5p9IzwY4Q==/6598140691041651067.jpg [4]: http://img0.ph.126.net/Bt48wZ1dql3vXkHeD13IpQ==/6598083516436988703.jpg [5]: http://img0.ph.126.net/wytmlqytiaqkvcuuWRzWWQ==/6598073620832357340.jpg [6]: http://img1.ph.126.net/7k2AisugvvojSqHiDWqjEQ==/6631355837750306431.jpg [7]: http://img2.ph.126.net/XW6aNnGO3c5F5vntrxHYZw==/6631261279750325570.jpg
        Speaker: Mr Hainan Liu (Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
        cv
        Paper
        Slides
    • 11:30 12:30
      Exhibition: Poster and Industrial Presentations
      • 11:30
        "On the design of a rad-hard signal conditioning ASIC for pressure module" 1h
        **European Sensor Systems** is a global developer and manufacturer of high quality sensors based on MEMS. In the course of the ESA activity 4000106328/12/NL/Cbi, European Sensor Systems is developing a “Space Qualified Family of MEMS Pressure Modules for Satellite Applications”. ![3D Model of Pressure Module][1] **Figure 1: 3D Model of Pressure Module** ESS has designed four MEMs sensors to cover the application’s pressure ranges (7, 22, 150, 310 bar) with dimensions 2×2×0.4 mm3 using X-FAB TM30P1111 technology, which is a combination of SOI, bulk and surface micro-machining process for the fabrication of capacitive pressure sensors. ESS is the IP owner and exclusive user of this process. ![Die photo of 22-bar MEMS][2] **Figure 2: Die photo of 22-bar MEMS** For interfacing with the MEMS, a custom radiation-hardened capacitive sensor signal conditioning ASIC has been designed. Based on the architecture of its commercial counterpart ASIC, ESS214 is built using X-FAB XH018 Process Design Kit, a 0.18 micron Modular Mixed Signal HV CMOS Technology. The output of the capacitance to voltage unit is converted to a 1-bit output by a second order ΣΔ modulator, which is down sampled and filtered in the digital part and finally converted to a 10-bit resolution PWM stream. The trimming of the device is performed via register programming using an I2C compatible Two-Wire Interface. A specific configuration can be written to the OTP memory once. The internal analog and digital regulator, the bandgap reference, the oscillator and the power-on reset eliminate the need of any additional components. Finally, a temperature sensor is embedded. ![ESS214 ASIC architecture and the MEMS interface][3] **Figure 3: ESS214 ASIC architecture and the MEMS interface** ![Microphotograph of the Fabricated ESS214 ASIC][4] **Figure 4: Microphotograph of the Fabricated ESS214 ASIC** In order to address the problem of SEE the Triple Module Redundancy method with voting has been adopted. This mitigation scheme uses three identical logic circuits performing the same task in parallel with corresponding outputs being compared through a majority voter circuit. The technique has been applied at the level of digital synthesis. The TMR technique has been applied to all flip-flops of the digital part. For SEL immunity in the digital part, a library of custom digital cells has been designed and characterized in house to enhance radiation tolerance. The library contains combinational, sequential and special cells (layout fillers, antenna protection cells) and was based on cells that already exist in the digital library D_CELLSL_JI3V, which contains triple-well junction isolated cells. The increase of the layout area compared to a conventional cell varies from 2x to 4x. The library has been seamlessly integrated to the IC design flow. In the analog part, all PMOS devices have been enclosed by N-type guard rings and all the NMOS devices have been enclosed by P-type guard rings. Regarding TID ESS214 is designed using standard cells. The CMOS ASIC has been tested for SEE (SEL/SEU) in the UCL cyclotron accelerator facility. The ASIC exhibited immunity to SEUs up to 32.4 MeV/(mg/cm^2) using Kr-769 and produced 2 SEUs at 62.50 MeV/(mg/cm^2) using Xe-995. The CMOS ASIC exhibited SEL immunity up to 62.5 MeV/(mg/cm^2) using Xe-995. The displacement damage test campaign is currently ongoing and results are expected soon. [1]: http://www.esenssys.com/ess/images/pressure-scaled.png [2]: http://www.esenssys.com/ess/images/mems-scaled.png [3]: http://www.esenssys.com/ess/images/ess214_func_blockdiagram-scaled.jpg [4]: http://www.esenssys.com/ess/images/asic-scaled.jpg
        Speaker: Mr Theodoros Athanasopoulos (European Sensor Systems S. A)
        Paper
        Poster
      • 11:30
        Radiation Hardened by Design Pipeline Analog-to-Digital Converter Blocks in CMOS 0.18µm Technology 1h
        CCD sensors embedded in satellites need not only to convert analog signals into digital ones with high precision and speed (around 14 bits at 5 MS/s) but also they must be radiation hardened due to the space environment. To achieve such performances, pipeline analog-to-digital converters (ADCs) are usually employed as it is shown in figure 1. ![Overview of the most used architectures depending on the required performances [Murmann2015]][1] The typical block diagram of a 1.5 bit stage for Pipeline ADC is shown in figure 2. ![A 1.5 bit stage for Pipeline ADC][2] From such architecture, the components that have the greatest influence on the ADC performances and the most sensitive blocks to radiations can be identified. Firstly, analog CMOS switches used in such ADCs suffer from both charge injection and drain-source resistance that depend on the input signal level. In addition, a sufficient overdriving voltage of CMOS switches might be difficult to obtain for low power supply voltage. Consequently, bootstrapped techniques are necessary but could not be applied directly for circuits operating in a radiative environment. We have thus proposed a bootstrapped switch architecture that avoids any overshoot voltage at any time (Fig.3) to prevent single event effects. It should ensure a greater radiation hardness of bootstrapped switch architectures. In particular, it was shown that some transistor sizes should be carefully chosen and a simple method to calculate them has been proposed [Bernal2014]. ![Proposed Bootstrapped Switch Schematic (proposed improvements in lighter tone) [Bernal2014]][3] Secondly, in order to improve further the reliability of the main stage amplifier and reduce its power consumption, a predictive amplifier based on a one-stage amplifier architecture was chosen and designed instead of a very high gain two/three stages amplifier. A correlated double sampling (CDS) [Nagaraj1987] has been used here to decrease errors from finite operational amplifier gain. It results in a predictive rail to rail amplifier with switched capacitances. Simulation results show that this technique has reduced by at least 4 times the amplification error of a pipeline stage compared to the non-predictive approach, which implies a 2-bits accuracy improvement. Finally, in radiation environment, comparators can have a high number of errors. We have implemented the radiation hardened approached proposed in [Olson2008] that aims to reduce the bit error rate of a comparator operating in a radiation environment (fig.4). It relies on a dual path design technique to reduce the vulnerability of floating nodes in the switched-capacitor input network of the comparator. Further, an auto-zero approach has been added up to reduce the comparator offset. ![Auto-zero comparator with Dual-path hardening around the preamplifier][4] To validate the performances given by simulation results, a bootstrapped switch and a classical one, an auto-zero comparator with dual-path hardening and a classical one, a predictive rail to rail amplifier with commutative capacitances and a single rail to rail amplifier, have been implemented in a 0.18µm CMOS process (fig.5). ![Die photograph of radiation Hardened pipeline ADC blocks][5] **Acknowledgments:** The authors would like to thank CNES and Thales Alenia Space for their financial support. **References:** [Murmann2015] B. Murmann, "ADC Performance Survey 1997 – 2015" [Bernal2014] Bernal, O.D. ; Perbet, L. ; Tap, H., “Radiation hardened bootstrapped switch in 0.18μm CMOS process, Electronics”, 21st IEEE International Conference onCircuits and Systems (ICECS), 7-10 Dec. 2014, pp 610 – 613. [Nagaraj1987] K. Nagaraj, “Switched-capacitor circuits with reduced sensitivity to amplifier gain,” IEEE Trans. Circuits Syst., vol. CAS-34, pp. 571–574,May 1987. [Olson2008] B. D. Olson et. al., “Single-Event Effect Mitigation in Switched-Capacitor Comparator Designs,” IEEE Trans. Nucl. Sci., vol. 55, No. 6, pp. 3440–3446, Dec. 2008. [1]: https://static.wixstatic.com/media/33c0ce_de3e4fd7d8954047b8eb855794fd1be2.jpg/v1/fill/w_600,h_370,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_de3e4fd7d8954047b8eb855794fd1be2.jpg [2]: https://static.wixstatic.com/media/33c0ce_ca13523667394405a94068ecddc7720e.jpg/v1/fill/w_600,h_293,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_ca13523667394405a94068ecddc7720e.jpg [3]: https://static.wixstatic.com/media/33c0ce_db7090a6251f44d2a6bfdd5f663f6d23.jpg/v1/fill/w_330,h_283,al_c,q_80/33c0ce_db7090a6251f44d2a6bfdd5f663f6d23.jpg [4]: https://static.wixstatic.com/media/33c0ce_500714262be94f4fa5f402e1250d4e98.jpg/v1/fill/w_600,h_225,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_500714262be94f4fa5f402e1250d4e98.jpg [5]: https://static.wixstatic.com/media/33c0ce_2ce7cb9100864fdb886e98dabd620dd5.jpg/v1/fill/w_340,h_255,al_c,q_80,usm_0.66_1.00_0.01/33c0ce_2ce7cb9100864fdb886e98dabd620dd5.jpg
        Speakers: Prof. Hélène TAP (INP-ENSEEIHT LAAS) , Dr Olivier Bernal (INP-ENSEEIHT LAAS)
        Paper
        Poster
      • 11:30
        Si and CdTe Detector Readout ASIC in 0.35µm CMOS for Energetic Electron Spectroscopy for Taranis 1h
        The compact size and power consumption of the electron energy detector instrument IDEE TARANIS requires the use of a dedicated ASIC readout circuit instead of discret devices for energy measurement. The ASIC consists of 8 CdTe, 4 regular size Si and 1 small Si detectors readout. Each channel includes a charge amplifier, a shaper, a peak detector and an 8-bit ADC. Si type channel covers the energy detection range of 70keV up to 700keV while CdTe channel covers the 300keV to 4MeV range. For a 40-pF detector parasitic capacitances, low noise performances are achieved: 3120e- for Si type channels and 2335e- for CdTe type channels. Low power performance of 2mW at 650-kHz frequency per Si channel and 2.9mW at 40-kHz per CdTe channel is achieved. While both type of channel share a similar design, CdTe type channel analog front end had to include a pole zero cancellation in order to achieve the required frequency of operation. The ASIC has been tested in standalone as well as interfaced with the detectors. Finally, the ASIC has been qualified with a heavy ion test. The ASIC has been implemented in AMS 0.35µm HV CMOS technology.
        Speakers: Mr Olivier Bernal (ENSEEIHT/INP - LAAS/CNRS) , Mrs king wah wong (CNRS - IRAP)
        CV
        Paper
        Poster
      • 11:30
        SOI CMOS Frequency Synthesizer for Flexible Communications Payloads 1h
        The COMS payloads, up and down link frequency and the bandwidth are all fixed during the lifetime of the satellite. But increasing satellite lifetimes of more than 15 years, the ability to adapt the payload to new scenarios such as flexibility would be highly advantageous. An agile-tunable Local Oscillator (LO) is the key components in the next generation flexible payload. In this reason, a study on a flexible LO is needed for the development of the next generation satellite payloads. The agile wide-band frequency synthesizer based on fractional-N PLL should be able to generate the wanted frequency within the wide band such as S-band, C-band, and Ku-band. Also, in order to design radiation hardened frequency synthesizer, we use design technique such as radiation hardening by design (RHBD), radiation hardening by process (RHBP), and radiation hardening by shielding (RHBS). To enhance phase noise characteristic in VCO, the current source is eliminated to reduce 1/f noise from bias line. But this architecture has other problems in VCO performance such as pushing and pulling figure, and process variation. So we use low drop-out (LDO) regulator with 2-bit output voltage control circuit in supply of VCO. Thus, output power and current consumption in VCO should be changed according to LDO. And this output current should also be fixed according to oscillation frequency and temperature variation to get stable phase noise performance. However, this circuit requires additional die area and noise source in LDO is not eliminated completely. PMOS cross coupled topology is used for VCO core circuit and using three VCOs to reduce VCO gain variation according to wide range of oscillation frequency from 4 GHz to 6 GHz. 5-bit switched MIM capacitor array in each VCO is used to cover oscillation frequency of 4 GHz to 4.6 GHz, and 4.6 GHz to 5.2 GHz and 5.2 GHz to 6 GHz, respectively. Due to stable operation of LDO, phase noise variation is within 2.4 dB over 1.6 ~ 2.0 V power supply and -40 ~ 85oC temperature range. VCO core including LDO draws 2.8 ~ 5.6 mA according to oscillation frequency from 1.8 V supply voltage. Frequency synthesizer consists of three VCOs, PTAT bias, LO generation block such as divider and buffer (or drive) amplifier, loop-filter and fractional-N PLL. The Σ-Δ fractional-N frequency synthesizer includes a 20-bit Σ-Δ modulator of third-order MASH type so that it achieves a fine frequency resolution of about 34 kHz. The charge pump using an analog calibration method with two op-amps eliminates output current mismatch. The external loop filter is used to optimize loop bandwidth each selected frequency bands. To calibrate loop bandwidth, the charge pump current and are programmable according to channel frequency. The prescaler including true single-phase clocked (TSPC) type D-type flip-flop (DFF) in N dividers has up to 1.5 GHz operations. The feedback divider consists of 10-bit pulse counter and 4-bit swallow counter. The integrated frequency synthesizer including three VCOs, LO generation block, bias, I2C, and fractional-N PLL occupies 5.0mm by 2.5mm. And this IC is fabricated using 0.18 μm RF SOI CMOS process.
        Speaker: Dr Seong-Mo Moon (Electronics and Telecommunications Research Institute (ETRI))
        notes
        Paper
      • 11:30
        Status of the GR718B Product - a Radiation-Tolerant 18x SpaceWire Router for Space Applications 1h
        GR718B is a radiation tolerant 18 port standalone SpaceWire router component that has been developed by Cobham Gaisler together with imec (BE), in an activity initiated by the European Space Agency under ESTEC contract 4000105402/12/NL/CBi.No. All ports are capable of operating in 200 Mbit/s. UART and JTAG interfaces, that gives access to the on-chip bus, are provided for configuration and debugging. SPI and GPIO interfaces are accessible through the configuration port, which allows SPI devices to be accessed and general purpose signaling to be performed through RMAP commands. In addition to the mandatory features in the current ECSS SpaceWire standard, GR718B supports group adaptive routing for path addresses, and packet distribution. It also includes support for the incoming SpaceWire standard revision 1 (ECSS-E-ST-50-12C Rev.1), the SpaceWire-D protocol, and the SpaceWire Plug-and-Play protocol currently being developed for ECSS. The technology used is UMC´s CMOS 180 nm, using the DARE library from imec, and the package is a 256 leads CQFP. The GR718B router is expected to withstand 300krad(Si) and is single event latch-up immune for linear energy transfer values above 118 MeVcm2/mg. The GR718B is currently being qualified for space applications following an ESCC9000 lot validation approach. Flight units will be available from January 2017. Prototypes and evaluation boards are already available.
        Speaker: Mr Fredrik Johansson (Cobham Gaisler AB)
    • 12:30 14:00
      Lunch 1h 30m
    • 14:00 14:40
      Radiation-hardened technologies for analogue and mixed-signal ICs: High Voltage
      Convener: Mr Olle Martinsson (Ruag)
      • 14:00
        Challenges of Designing a Radiation Tolerant Motion Control System on Chip 20m
        There are many applications for motion control in space. The application may require rotational torque or linear force in addressing such system functions such as antenna pointing, solar array positioning, robotic arms and control valves. A versatile design is needed to address as many applications as possible with a new integrated circuit so that the initial research and development investment can be recouped. IC developments are typically upwards of several hundred thousand US dollars. A versatile motor control design can be used for different types of synchronous motors such as stepper motors, brushless DC motors, and torque motors. A versatile position sensor will interface to resolvers, synchros, linear variable differential transformers (LVDT), potentiometers, optical sensors, and limit switches. The first step in partitioning a versatile design approach is to look for the common elements in all the different applications. All motors require switches to regulate current to the motor coils, many applications require a pulse width modulated switch in a half bridge configuration. N channel MOSFETs are typically better performing than P channel but require a floating high side driver. All closed loop motor control algorithms require current sensing; variations include power line sensing, ground current sensing and motor terminal current sensing. For the most versatility, the current sensing should be floating and configurable. Position sensors such as resolvers or LVDTs consist of a transformer primary driven by an exciter reference. The transformer secondary must be sampled to extract the position information. In order for the motion control system to be versatile, a customized programming algorithm must be adapted to each case. A programmable controller can consist of a DSP that executes sequential instructions or it can be an FPGA with the ability to process multiple data pipelines simultaneously. The motion control function can be broken down into three specific IC requirements. A high voltage IC process such as a 1.0um, 350V, trench isolated BCD process is needed for interfacing to the motor switches and current sensing; typical spacecraft systems are powered from voltage sources that range from 12V to 150V. A low voltage, 0.6um, BiCMOS IC (5V) process is needed for signal processing and could also be used for some moderately dense logic. Specialized proprietary design techniques and circuit models are required to make use of processes that might otherwise not be radiation tolerant. The signal processing portion requires a small geometry process such as 65nm that can implement hundreds of thousands of gates. The signal processing portion can utilize radiation tolerant devices such as FPGAs that are “off the shelf”. The high voltage and low voltage analog silicon chips can be co-packaged as a device that appears from the pins out to be a single IC even though it contains two chips. A technique of wire bonding between the chips has been demonstrated successfully in production. This two chip approach is still considered an IC by the Defense Logistics Agency. This co-packaging of chips exploits the advantages of each process. The use of a radiation tolerant FPGA alongside a versatile analog front end as its companion chip is the essence of our “System Manager” total system approach. An example of a function that is partitioned between the three different ICs in this system is the floating current sense. The floating current sense uses the dynamic range of the high voltage IC to interface to the current sense resistor. There is an initial gain stage implemented in the high voltage process that feeds its output to an instrumentation amplifier implemented in the 5V process. The 5V IC shares the same signal ground with the FPGA. Once level shifted from floating high voltage to a signal ground referenced, the analog signal is sampled using a second order sigma delta modulator implemented in the BiCMOS process. The lower voltage process can implement functions in less space due to the smaller geometry. The output of the modulator is a “ones density” data stream that is voltage compatible with the FPGA. The data stream consumes just one package pin as it is routed between the analog front end (AFE) and the FPGA. In the FPGA a specialized IP block performs a sinc3 filter and decimation function. In the FPGA this can be done at a speed that could not be supported in the AFE 5V process. This pipeline from sense resistor to FPGA control loop takes full advantage of the unique capabilities of each of the ICs it passes through. The digital signal processing of the motor control function can be partitioned into functional blocks to provide the greatest level of IP reuse. Functions can be added or removed to an application depending on what type of control algorithm is needed. Individual blocks can be customized by setting variables. An example of this is the setting of the decimation rate in the sinc3 filter IP block; signals with a higher oversample rate will have higher resolution at the cost tradeoff of longer latency. A CAD design tool such as Libero SoC allows blocks to be configured and customized. Radiation tolerance for this design will be demonstrated by testing for total dose, ELDRs and Single event upset immunity. The same fabrication process and design techniques for the motion control system analog front end were used to develop the LX7730 64 channel telemetry manager ICs; this part was confirmed tolerant of a 100krad total dose and SEU up to a fluence of 1e8 part/cm2 and linear energy transfer of 87.85 MeV/mg.cm2.
        Speaker: Mr Bruce Ferguson (Microsemi)
        Bio for Mr Ferguson
        Paper
        Slides
      • 14:20
        RADIATION HARDENED HIGH-VOLTAGE AND MIXED-SIGNAL IP WITH DARE TECHNOLOGY 20m
        Recent trends show the growing need for more analog, mixed-signal and high-voltage IP to enhance the intelligence and reduce the cost of satellites. This paper presents the set of radiation hard, mixed-signal and high-voltage IP that is part of the imec DARE solution and that is developed in UMC 0.18um, XFAB XH018 and On Semiconductor i3t80 technology. The IP is conceived to enable rad-hard SoC developments and consists of ADCs, PLLs, clocks, linear regulators, bandgap references with current reference and temperature sensors, high-voltage DCDC converters to convert the satellite main supply to analog and digital on-chip voltages and several high-power and high-voltage switches and drivers for a.o. HPC (high-power commands). The IP is versatile to be useful in a myriad of applications and is part of the DARE platform. The IP in UMC 0.18um has been successfully silicon proven and radiation tested. First-time-right radiation hardness is achieved through a proprietary under-radiation simulation approach developed by ICsense and elaborated in this paper.
        Speaker: Dr Bram De Muer (ICsense)
        Paper
        Slides
        summary
    • 14:40 15:20
      Full custom digital, analogue, or mixed-signal: Receivers and Transmitters (1/2)
      Convener: Mr Steven Redant (IMEC)
      • 14:40
        Octal LVDS Repeater Test Results 20m
        The purpose of this paper is to present the electrical and radiation results of the tests performed on the LVDS Octal repeater developed by ARQRUIMEA in the frame of ESA’s and ECI’s European LVDS Driver Development intended to be used in space applications and built in IHP’s 0.25-um BiCMOS process technology. The key features of the octal LVDS repeater include cold sparing, more than 250MHz signaling rate per channel allowing more than 500Mbps transfer rates over SpiceWire, 3.3V single power supply, low channel to channel skew, TRI-state output control, extended common mode on LVDS receivers and t ESD tolerance up to of 8kV for human body model The Octal LVDS repeater has been tested up to 300Krad without important degradation. Additionally, the devices have shown no sensitivity to Latch-up up to the maximum tested LET of 62.5 MeV cm2/mg. The octal repeater is not sensitive to SET or SEU up to 20 MeV cm2/mg. At higher 62.5 MeV cm2/mg 15 bit errors were detected after 1012 transmitted bits.
        Speaker: Mr Jesús López (Arquimea Ingeniería S.L.U)
        notes
        Paper
        Slides
      • 15:00
        SEPHY: An Ethernet Physical Layer Transceiver for Space 20m
        Since its development, Ethernet has experienced an impressive growth and has become the dominant technology for wired local area networks. It has also more recently expanded beyond computer networks to cover also industrial and automotive networks. This adoption is driven by the lower costs enabled by reusing existing technology. For critical applications, Ethernet has to be extended to ensure timely and reliable delivery of frames. A number of technologies that can solve the reliability and real time issues have been proposed, for example Time Triggered Ethernet (TTE). Space systems are an example of critical applications and Ethernet has been used in some missions like NASA´s Orion and in launchers. However, there is an additional problem in space applications that has so far prevented a wider adoption of Ethernet. Electronic circuits that operate in space are exposed to radiation that causes errors and make most commercial devices not suitable for space missions. This means that special components have to be designed for space use. For Ethernet, most components like switches or Medium Access Controllers (MACs) are purely digital. There is however one exception, the physical layer transceivers (PHYs) that are by nature mixed-signal devices. The availability of rad-hard Ethernet PHYs qualified for space use is crucial to enable the widespread adoption of Ethernet in space. This paper presents the options for a space Ethernet PHY and the SEPHY project that is currently developing a 10/100 Mb/s European Ethernet transceiver for space. **Options for a Space Ethernet PHY** The IEEE 802.3 standard defines many PHYs covering different transmission media and speeds. The most commonly used media in Ethernet are Unshielded Twisted Pairs (UTP). Assuming that the space PHY will use UTP, the IEEE 802.3 standard provides several alternatives. The most relevant ones are: 10BASE-T defined in IEEE 802.3i , 100BASE-TX defined in IEEE 802.3u, 1000BASE-T defined in IEEE 802.3ab and 10GBASE-T defined in IEEE 802.3an. Each of those standards provides a 10x speed increase over the previous one, starting with the 10 Mb/s of 10BASE-T. From a performance point of view, the best would be to select the highest speed PHY for rad-hard implementation. However, there are other factors that should be considered when making a decision. As the speed increases, so does the complexity of the PHY. For example, 10GBASE-T PHYs are currently manufactured in 40 or 28 nm technologies and consume several watts. Implementing that PHY on the older nodes qualified for space use will most likely not be feasible. The development cost also increases with speed. Therefore, the selection of the PHY standards to implement for the space market needs shall weight both the speed and the cost/complexity. The first standards (10BASE-T and 100BASE-TX) use only two pairs in half duplex mode. Therefore, there is no echo and no far-end crosstalk. This greatly simplifies the transceiver design. For 100BASE-TX the speed increase is achieved by using a larger transmission frequency and number of levels. In any case both standards can be implemented with a moderate cost on an old technology node. On the other hand, the 1000BASE-T and 10GBASE-T standards use the four pairs in full duplex. This means that the receiver on each pair needs to cancel the echo and the crosstalk from the other three pairs. Additionally, these two standards incorporate a more sophisticated coding scheme (Trellis Code Modulation in the first case and Multilevel Coset Coding in the second) that need complex decoders. This makes the implementation of the transceiver a challenging task. **A European Ethernet transceiver for space: SEPHY** The Space Ethernet PHYsical layer transceiver (SEPHY) project funded by the European Union Horizon 2020 research program, is currently developing a radiation hardened PHY. The availability of a European PHY is key to ensure that access to the PHY is not restricted by the United States International Traffic in Arms Regulation (ITAR) and the Export Administration Regulation (EAR), and as a consequence, the non-dependence for the European space industry is guaranteed. The goal of the project is to deliver a production-worth PHY in 2017. The technology selected to implement the SEPHY device is Atmel´s 150 nm Silicon On Insulator (SOI), as it provides a sufficient level of radiation tolerance that qualifies it for space applications. It is also the same technology for which other European Ethernet components are being developed in the FLPP3 Time-trigered Ethernet Space ASIC project. The project consortium is formed by different European companies and research centers led by Arquimea that will develop the analog components. IHP will focus on the digital design and Universidad Antonio de Nebrija on the verification. Atmel will be in charge of the fabrication of the integrated circuits. Finally, TTTech and Thales Alenia Space Spain will integrate and test the silicon prototypes on a network and perform also radiation testing. The project targets the implementation of the 10BASE-T and 100BASE-TX standards. This will provide 10Mb/s and 100Mb/s connectivity in space systems. This compares to the solutions currently used in the space domain like the Mil-Std-1553B (low data rate, large cable length) or SpaceWire (high data rate, short cable length). The proposed transceiver will meet the cable length (100m) and data transfer (100Mbps) requirements not only for launchers applications where cable length is the main constraint but also for the onboard communication requirements where high data rate is required. Those standards can be likewise implemented with a reasonable cost and provide a solution to the industry needs in the short term. The development of a 1000BASE-T PHY would imply much larger cost, time and risk and could jeopardize the adoption of Ethernet. Additionally, starting with lower speeds gives the opportunity to the new standards being developed to mature potentially providing more choices for the second generation of SEPHY. In fact, the project also includes a roadmap activity to identify the best alternative for a second generation of SEPHYs. This will target at least 1Gb/s and its feasibility will also be studied and linked to the future technology nodes planned for space devices. **Acknowledgements** This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No.64024.
        Speakers: Mr Daniel Gonzalez (Arquimea Ingenieria S.L.U) , Mr Jesús López (Arquimea Ingenería S.L.U)
        notes
        Paper
        Slides
    • 15:20 15:50
      Coffee 30m
    • 15:50 17:10
      Full custom digital, analogue, or mixed-signal: Receivers and Transmitters (2/2)
      Convener: Steven Redant (IMEC)
      • 15:50
        A 2.56 Gbps Radiation Hardened LVDS/SLVS Receiver in 65 nm CMOS 20m
        Many of today's applications require high precision time-domain signal processing circuits like particle detectors in high-energy physics experiments such as the CMS and ATLAS experiments at the Large Hadron Collider (LHC) in CERN or laser-ranging sensors. The key information of these applications is contained in the timing difference between multiple signals or events. This timing information is usually converted to binary data using time to digital converters (TDC). In large and/or complex systems however, the distance between the detector/event generator and the TDC can become rather large, calling for a highly time accurate, long distance, transfer of these signals. Many applications now use Low Voltage Differential Signaling (LVDS) and Scalable Low Voltage Signaling (SLVS) for data transmission because of its robustness to interferences, low power consumption and high speed. The SLVS standard is comparable to the LVDS standard, with the difference of a 200 mV common mode voltage and 200 mV voltage swing instead of 1.2 V common mode and 400 mV swing. For data transmission applications, the regenerative nature of the receiver allows some tolerance to jitter provided the bit error rate remains low. However, in the envisaged sub-nanosecond timing applications, jitter is the major impairment to the performance of the system. When an LVDS/SLVS receiver is used in the signal path between the event generator circuit and the TDC, any time distortion introduced by the receiver, will cause a time measurement error and consequently will lower the system resolution. To allow an accurate time measurement, the propagation delay of all the edges, at the output of the LVDS/SLVS receiver, must be the same. This paper focuses on the design of a radiation hardened by design LVDS/SLVS receiver which can be used in high resolution time measurement applications. This design uses a NMOS input pair, single ended output op amp structure where the output currents can be tuned in order to achieve an equal propagation delay between the rising and falling edges at the output of the receiver. In radiation environments, the total ionizing dose (TID) will change the gain/propagation delay of the receiver, due to shifts in the threshold voltage and degradation of the charge carrier mobility. This will introduce a propagation delay mismatch between the rising and falling output edges. To compensate this mismatch, a replica receiver is added which is capable of measuring the difference in propagation delay between the two edges. When the propagation delays of the rising and falling edges are equal, an ideal clock at the input of this replica receiver must generate a clock signal at the output with a duty cycle of 50 % and a common mode voltage of $V_{DD}/2$. Any mismatch in this duty cycle, caused by the TID effects, will be measured by the integrating feedback loop and will be used to adjust the currents through the receiver in order to equalize the propagation delays of the output rising and falling edges. The proposed receiver is designed and simulated using a commercial 65 nm CMOS technology. This technology has a power supply of 1.2 V which is identical to the common mode voltage of an LVDS signal. In this design, for an optimal use of the NMOS input pair receiver, the common mode voltage of the input signals must be between $\pm$ 0.5 V - 1 V. This is fine for ad-hoc systems, like the CMS and ALTAS detectors at CERN, which don't need to communicate with off-the-shelve LVDS modules, and so can freely choose the common mode level. Nevertheless, the proposed technique is easily scalable to I/O devices or other technologies with a larger power supply for full LVDS compatibility. Additionally, a PMOS input pair receiver is designed which is able to receive low common mode voltage and SLVS signals. The proposed receiver is capable of supporting event rates equivalent to a 2.56 Gbps data rate with less than 400 fs output RMS jitter and 500 $\mu$W power consumption from a 1.2 V power supply.
        Speaker: Mr Bram Faes (KU Leuven)
        Paper
        Slides
        summary
      • 16:10
        European LVDS Development - current status 20m
        The integration of a dual LVDS receiver and transmitter into one package, meeting the space radiation, cold-sparing and capable of handling large common mode signals, is a necessity to meet the increasing demand for robust SpaceWire communication in satellites. In the frame of an ESA activity under the European Component Initiative (ECI) program, Cobham-Gaisler has undertaken the development of such LVDS transceiver, ideally suited for SpaceWire links, to complement its product range of SpaceWire products. The scope of the LVDS transceiver development will be presented together with the architecture of the LVDS transceiver. The specific implementation issues pertinent to the reliable operation of the SpaceWire link operation in space like the receiver input hysteresis, embedded active fail-safe circuitry, cold-spare and 8kV ESD protected IO's in addition to applied radiation mitigation methodology will be discussed. Finally the relevant prototype electrical and radiation test results will be presented.
        Speaker: Mr Fredrik Sturesson (Cobham Gaisler AB)
        summary
      • 16:30
        Radiation Tolerant CAN Transceiver for Space 20m
        The severe -2V to 7V common-mode and -3V to 16V failure tolerance requirements of the CAN bus have restricted its implementation to high-voltage processes with transistors tolerant to voltages above 16V. This paper demonstrates for the first time that a CAN transceiver can also be realized with standard 3.3V 350nm CMOS double and triple well devices available in Mixed Mode 180nm CMOS technologies. This leads to lower power consumption, lower bus port capacitances and facilitates integration with the CAN controller and large digital circuits, while for space provides higher radiation tolerance.
        Speaker: Dr Richard Jansen (ESA)
        Paper
        Slides
        summary
    • 17:30 22:15
      Cruise of the Göteborg Waterways

      A local guide will describe the sights of the city with seating available below and on the deck of the M/S St Erik, (named after Erik IX; King of Sweden late 1150) docked at the Göteborg Harbor - bring your camera!

      • 17:30
        Meet in the hotel lobby to walk to the harbor 15m Gothenburg, Sweden

        Gothenburg, Sweden

      • 17:45
        Arrive at Göteborg Harbor and board M/S St Erik 15m Gothenburg, Sweden

        Gothenburg, Sweden

      • 18:00
        Cruise begins 30m M/S St Erik

        M/S St Erik

      • 18:30
        Departure 1h 15m Cruise (Gothenburg, Sweden)

        Cruise

        Gothenburg, Sweden

        Depart boat for Nya Älvsborgs Fästning tour. Your arrival at Nya Älvsborgs Fästning (Fort) will be welcomed with a cannon blast. The fortress on Kyrkogårdsholmen (Cemetary Island) at the entrance of Göteborg harbor, began construction in 1653.

      • 19:45
        Cruise 2h 15m M/S St Erik (Gothenburg, Sweden)

        M/S St Erik

        Gothenburg, Sweden

        Reboard the M/S St Erik and cruise to the River Café for dinner

      • 22:00
        Bus return to Hotel 15m Gothenburg, Sweden

        Gothenburg, Sweden

    • 08:30 09:00
      Registration 30m

      Open from 8:30 to 17:00

    • 09:00 09:20
      Keynote Speech
      • 09:00
        First Telecom Application of Digital and Mixed Component Developments:65nm ASIC and Data Converters 20m
        First we will give an overview of Digital Transparent Processor (DTP) development in the frame of FAST project. The DTP is a key element of TAS SpaceFlex processor. DTP development is targeting both commercial and defense satellites. New generation of DTP is able to address high bandwidth, with high capacity with a cost decreases in mass, power consumption and volume per GHz. Then we will report on the key technologies for DTP. It’s about first 65nm ASIC from TAS-Atmel-STMicroelectronics and E2V data converters. To address the need of high integration, low power consumption, 65nm ASIC offer was developed by ATMEL and STMicroelectronics with CNES and ESA support. This offer incorporates HSSL link. First ASIC was designed by TAS and called VT65. VT65 ASIC was manufactured by Atmel, ST and E2V, using flip-chip technology. VT65 tests are now completed and results are in line with the target. With CNES support, E2V has designed high speed, large input bandwidth, low power data converters. EV12AD550 ADC ESCC evaluation is started and first test results will be presented, showing very good performances. EV12DS130A DAC is now used in Telecom space programs. To conclude DTP is a high tech product with high innovation, for drastically enhanced performances, thanks to a constructive collaboration between all the FAST partners, Telecoms, Technologists, Components engineers and Manufacturers.
        Speaker: Mrs Florence Malou (CNES)
        Slides
        summary
    • 09:20 10:00
      Evaluation and qualification of full custom ICs for space applications
      Convener: Mrs Florence Malou (CNES)
      • 09:20
        Design Methodology for mixed signal ASIC with prequalified Analog IPs for space applications 20m
        Mixed Analog / Digital System on Chip are increasing drastically in space equipment to reduce cost, power and dimensions and to improve performances. The challenge for mixed SoC is to get a qualified product without heavy SEE or TID testing. As for a digital library, analogue cells and their combinations, High voltage LDMOS, regulators (to allow single supply) and latch-up protections must be “pre-qualified”. The qualification of IOs and digital is done by using a Standard Evaluation Circuit covering at least half of the maximum of transistor of an ASIC. For the analog part all blocks must be validated. In addition, in order to check the “integrability” of the building blocks towards the elaboration of a complex space-adequate System-on_Chip, a complex function will be realized embedding all individual analog cells and a digital block embedded as an analog cell. During the realization of this complex function emphasis is given to the observability and testability of the individual building blocks. For each new analog cell the same process must be conducted. The study will continue by determining the observability of the analog nodes and specifically the eventual propagation of Single Event Transient. This study is conducted with support of ESA and CNES and with European industrial partners. ATMEL ATMX150RHA offers a wide range of capabilities to enlarge the SoC integration: digital integration up to 20M gates, NVM, analogue, 3Gbit serial interface, N and P deep well, Deep Trench to isolate blocks, handle Wafer contact, 1.8V digital core, 3V, 5V, 15V and high voltage up to 60V. Mixing power, high voltage and high speed on a single chip needs adequate packaging technology, large die and small die must be handled by different packaging solutions: double pad ring, flipchip, Au bonding, Al bonding. ATMEL can base the qualification for space requirements on standard process used in high volume. It ensures longer process lifetime and stability, as well as lower access cost. Same advantages applies to probe, assembly and final test. A mixed Standard Evaluation Circuit is under definition in order to check the “integrability” and “space testability and observability” of the building blocks. The flow and the rules for integration of analogue cells coming from multiple suppliers will be clearly defined and qualified. Key words: mixed Soc, embedded NVM, high voltage LDMOS, mixed MPU, mixed MCU
        Speaker: Mr Bernard BANCELIN (ATMEL NANTES S.A.S.)
        Paper
        summary
      • 09:40
        Approval Process of an ESCC Qualified ASIC Supply Chain based on a Mixed-Signal IP Library 20m
        A fast and reliable development of a Rad Hard Space product benefits on a dynamic and efficient way of an ASIC design and supply chain. Design and qualification of a new ASIC is associated with a long development phase. Using an ESCC qualified IP library for the ASIC can reduce this development phase significantly and lowers the costs of the product. This supply chain resolves the trade-off between a full custom design with all associated qualification steps and a semi optimized product based on standard ICs. IMST and TESAT Spacecom are currently working in a DLR funded R&D project to built up such an ASIC supply chain that will be offered by IMST after approval by ESCC consortium. Completion of this project is planned for Q1 2017. A first publication of this ASIC supply chain establishment has been given on the AMICSA 2014 in CERN with the title: 180nm CMOS Mixed-Signal Radiation Hard Library as base for a full ASIC supply chain Now an update will be given on the current status of this project with measurement results including TID and SEE evaluation. The designed Library elements will be presented and an overview of the supply chain will be given with all supported technology features, package choices and the design flow information. The radiation hardened library designed by IMST, called HARD Library (HARD= Hard Against Radiation Design) is built on the XH018 180 nm CMOS technology from XFAB. It supports I/O cells for 3.3 V and 5 V supply as well as level shifter I/Os for a negative supply voltage of -5 V on the ASIC. The other IPs are specified with the intention to cover a wide range of applications. The IP library contains data converters, biasing cells, memory modules, a reconfigurable opamp, LVDS driver and receiver, SPI interface, OTP cells, clk PLL, oscillators and special I/Os with cold spare functionality. A ceramic quad lead frame package family has been developed for the supply chain with different pin counts from 32 up to 256, supporting die sizes from 1.5 X 1.5 mm^2 for the smallest package up to 10 X 10 mm^2 for the largest package. Two main design flows are targeted: One is a turn-key design by IMST based on customer requirements, while the other flow assists a co-design with the customer where the customer is allowed to provide encrypted VHDL codes. In the latter case IMST is creating the netlist with selected digital standard cells and implements TMR structures in order to guaranty a Rad Hard design. Analog features are handled by IMST using the IP library. On either case IMST delivers a tested, qualified and assembled Rad Hard ASIC.
        Speaker: Mr Jan Steinkamp (IMST GmbH)
        Paper
        Slides
        summary
    • 10:00 10:40
      Radiation tests of analogue and mixed-signal ICs
      Convener: Mr Fredrik Sturesson (Cobham Gaisler)
      • 10:00
        The pros and cons of in situ testing - going beyond the test standards 20m
         The pros and cons of in situ testing – going beyond the test standards Richard Sharp and Jiri Hofman, Cobham RAD Solutions Abstract— This paper discusses the benefits of in situ testing compared with the common practice of remote testing at a small number of total dose steps. INTRODUCTION TOTAL dose radiation testing of electronic components for use in space environments is frequently carried out according to one of two test standards: either ESCC 22900 [1] published by the European Space Agency or Mil-Std-883, method 1019 [2]. Both of these standards were written around the basic concept of alternately making electrical measurements on the components and then irradiating them. Numerous instances have subsequently been noted where this could lead to an erroneous understanding of the response to radiation exhibited by the components being tested. This paper highlights the issues associated with some of those instances and proposes in situ testing as an alternative test strategy that, in certain circumstances, can lead to much greater fidelity of the results and higher confidence in the validity of the data gathered. I. EXISTING TEST STANDARDS ESCC 22900 describes the basic requirements applicable to total dose radiation testing of integrated circuits and discrete semiconductors suitable for space environments. It distinguishes between in situ testing, where electrical measurements are made on the devices under test (“DUTs”) which are physically located in the irradiation chamber, and remote testing, where the DUTs are removed from the chamber for the measurements to be made. In situ testing is permitted either during or after irradiation. However, the majority of the document assumes that remote testing will be carried out with multiple, discrete radiation exposures and, hence, will yield data points at only a few values of total dose. Mil-Std-883, method 1019 (and Mil-Std-750, method 1019 is very similar) uses the term ‘in-flux’ testing in place of ‘in situ’. The standard states that not-in-flux testing allows for more comprehensive electrical testing but may give misleading results if significant post-irradiation time dependent effects occur. In situ testing is permitted but, again, the remainder of the standard is written assuming that remote testing will be carried out. In practice, the majority of tests are carried out using remote testing and just a few total dose steps. Both standards define time limits that should be observed so as to minimise post-irradiation time dependent effects that may cause parameter values to shift significantly from their immediate, post-irradiation values. However, the guidance given in both standards regarding the number of dose steps and their spacing is sparse and different. ESCC 22900 specifies that measurements shall be made at a minimum of three dose steps and that these shall be set at “1/3, 1 and 3 times the radiation level of interest”. Mil-Std-883 method 1019 provides no guidance at all on the number of dose steps and requires irradiation above the radiation level of interest only for certain technologies and in low dose rate conditions. One dose point would be sufficient to meet these requirements although, in practice, up to six dose steps are frequently applied. Having considered these provisions of the two standards, it is worth noting that many tests deviate from one or more aspects of the standards. This may be because the application has some features that justify a variation from the standard or because previous data have influenced the test plan. The impact of this deviation on the measurement technique should be assessed. II. A DESCRIPTION OF THE IN SITU METHOD In situ (or in-flux) testing requires the measurement system to be included in the signal chain during exposure of the DUTs to irradiation. This may require the switching in and out of multiple test instruments and more than one bias condition to be applied to the DUTs. Disadvantages of the in situ method There are several disadvantages to the in situ method, including complexity of the electrical circuit, relatively long lead lengths, restrictions on how close instrumentation may be placed to the DUTs, radiation effects on the measuring system and potential issues with processing large amounts of measurement data. The primary issue is ensuring that the fidelity of the measurement process is maintained throughout the test by avoiding any influence of radiation on the measuring instrumentation. This may be achieved by placing the instrumentation outside the radiation area. However, leads of more than 10m in length may be required, complicating the measurement of very low voltages and currents and making high speed measurements very difficult indeed. Alternatively, instrumentation may be located close to the DUTs and protected by shielding. The amounts of shielding required can be cumbersome and installing it may present a physical risk to the test equipment and personnel. Some electrical tests simply cannot be carried out in situ. These include parameters for which a large or complex measurement system is required, especially for sophisticated digital parts, such as microprocessors. Nevertheless, in these cases, in situ measurement of a parameter even as simple as the supply current can yield valuable information about the radiation response of the device. A secondary issue relates to how the measuring system is set up. It is possible to generate large quantities of data, most of which, for slowly changing parameters, may be of little value. Some planning of the data collection strategy can significantly reduce the post-irradiation analysis effort. One further issue to consider is the impact of frequent measurements using bias conditions different from those applied between measurements. This can lead to a difference in the measured effects compared to a test carried out using remote testing. Advantages of the in situ method The main advantage of in situ testing is that the greater quantity of data gives much finer resolution of the effects of the radiation exposure as measured on the total dose scale. Subtle and non-linear effects are more readily identified with in situ testing. An example of this phenomenon is shown in section III below. In situ testing also helps to avoid errors due to time dependent effects occurring after irradiation and before measurement. The measurement system can continue running after the radiation source has been withdrawn, providing data from the point in time immediately after irradiation has ceased. This gives a detailed picture of the magnitude and rate of annealing effects. In any real application, the circuit in which the DUT would be deployed would experience the impact of the radiation exposure during and immediately after the exposure. In situ testing more closely mimics this situation than remote testing. In order to benefit fully from these advantages of in situ testing and especially for long duration tests, it is important to remember the value of measurements on a control device for validating the stability of the test set-up. III. CASE STUDY An example is given here for the total dose testing of a voltage reference device. The test was instrumented in situ to measure the output voltage of three DUTs. The DUTs were irradiated with static bias and at a dose rate of 447 rad[Si]/hr in Cobham’s cobalt-60 gamma irradiation facility at Harwell, UK. Fig. 1 shows a graph of the change in output voltage when measured at a series of dose steps of 50, 200, 250 and 300krad. It can be seen that the primary trend is for the measured value to decrease with increasing total dose. Based upon these data, a circuit designer may allow for a reduction of a certain percentage in the output voltage. Fig. 2 shows the same data measured in situ at one minute intervals. Several features are visible. Firstly, the traces are much smoother, simply due to the finer dose resolution. Secondly, a significant rise in the output voltage is visible between 50 and 100krad, followed by an even larger reduction between 125 and 200krad. This feature is not visible in the first set of data because of the dose steps that happened to be chosen. With this additional information, the circuit designer would make a completely different allowance for shifts in the output voltage. Fig. 1. Output voltage against total dose with data at four dose steps. Fig. 2. Output voltage against total dose with the full in situ data. IV. DISCUSSION The experimental data show that, in the case of a nonlinear response to radiation exhibited by a given parameter, a data acquisition system based upon in situ measurements can reveal unexpected behaviour and yield valuable insights to the induced changes. The complex nature of this response may be missed by remote testing and a test regime using a small number of dose steps. Where remote testing is used, care is required in selecting the dose steps to reduce the probability of such a response being overlooked. An in situ test on one or two DUTs may be a useful screening technique to employ before a full test is carried out. CONCLUSION The in situ method is not applicable to all types of device or all parameters, especially where high speeds or frequencies or very low voltages or currents are involved. However, DC and low frequency signals lend themselves readily to in situ monitoring and the additional data obtained, coupled with the greater total dose resolution, can lead to a much better understanding of the effects of irradiation on the samples. REFERENCES [1] ESA ESCC Basic Specification No. 22900, “Total dose steady-state irradiation test method”, issue 4, October 2010 [2] Mil-Std-883, method 1019, “Ionizing radiation (total dose) test procedure”, issue 1019.9, June 2013
        Speaker: Dr Sharp Richard (Cobham RAD Solutions)
        notes
        Paper
        Slides
      • 10:20
        Total Ionizing Dose Testing of Solid State Power Amplifiers 20m
        Radiation testing of in-house developed GaAs-based Solid State Power Amplifiers (SSPAs) operating at super high frequencies (SHF) has been performed with a Co-60 source. GaAs-based electronic components are considered to be generally immune against Total Ionizing Dose (TID). Test results are presented here to quantify residual performance degradations of these SSPAs at various total ionizing doses and other extreme environmental conditions.
        Speaker: Prof. Melahat Bilge DEMIRKOZ (Middle East Technical University)
        Paper
        Slides
        summary
    • 10:40 11:10
      Coffee 30m
    • 11:10 12:10
      Radiation Effects on analogue and mixed-signal ICs
      Convener: Mr Fredrik Sturesson (Cobham Gaisler)
      • 11:10
        FPGA Radiation Hardening by Design in CMOS65nm 20m
        In a radiative environment, when a particle with a given LET (Linear energy transfer in MeV.cm²/mg) hits the substrate of a circuit, it creates electron-hole pairs along its braking track; this causes current injections between junctions and consequently upsets node voltages. These transients are called SETs (Single Event Transient). For digital circuits like the FPGA core, a SET corrupts the data as it makes a sequential bit to flip. Due to technology down-sizing and reduction of supply voltage, circuits become even more sensitive to radiation. This work is implemented in ST CMOS 65nm process. In order to improve the reliability of our FPGA, dedicated to the applications in radiative environments, our full custom library have been simulated using IROC software (TFIT). TFIT calculates the currents injections and simulates their effect by running SPICE simulation. During the hardening process, two kinds of studies were carried out: • The Single Event Upsets (SEU) that is a direct upset of a sequential logic (configuration of SRAM and Digital Flip Flop (DFF)). For SRAM, the cell under study with the smallest capacitive load was considered as the worst case. • The Single Event Transient (SET) in the clock and reset networks can have 2 effects: Jitters that occurs at the clock edge and the glitches that occurs between the clock edges. These effects can make a bit error to propagate in DFF. The design efforts are put on the glitches considering a static clock. Thus we are in a worst case situation in which jitters are replaced by glitches. Moreover, in our designs, Jitter occurs rarely compared to the glitches. This is because minimum period of a clock is 5ns whereas the SET duration is less than 300ps for a LET less than 58 MeV.cm²/mg in normal incidence. Besides, an upset on reset signal can reset a DFF storing “1”. The smallest clock glitch to write in DFF is 150ps. Hence the glitches longer than 150ps are considered as a SET error. No capacitive and resistive load is added in order to simulate the worst case of the cross section. SEU and SET effects are studied and radiation hardening is performed on all the library cells that are sensitive to these effects: • SEU in configuration memory: configuration memory of our SRAM based FPGA; they are very critical and require a high level of hardening. • SET on clock/reset buffer and matrix: they propagate clock and asynchronous or synchronous reset into the circuit with a low skew. • SEU/SET Digital Flip Flop: user register. In order to improve the reliability, design optimization are made on structure and layout by calculating upset current with TFIT and running SPICE simulation for different positions (step 50nm) and incidence angles (3 tilt angles x 8 rotation angles). TFIT software give an estimation of the normal and average angular cross sections. The cross section represents the whole sensitive area (normal to the incidence) through which a particle impact causes an SEU/SET. Thus the cross section of the structures is reduced by alternately improving layout and running simulation under 1.08V, lowest supply voltage, typical corner and 25°C. The layout is optimized by putting more distance between sensitive nodes and by bringing the tap closer to them. The results of worst cross section among the different states for the different cell show a great improvement of the radiation hardness.
        Speaker: Mr Quentin CROENNE (Nanoxplore)
        Paper
      • 11:30
        Radiation Prediction Tool Dedicated to Analyzing and Hardening by Design readout circuits of photonic ICs 20m
        **1. Introduction** Image sensors are widely used in spacecraft for many applications [1] [2]. Photonic imager technology has been developed for wavelength responses that range from ultraviolet, through visible, to infrared. Most radiation effects studies have been made on infrared detectors, and visible/near infrared technologies such as charge coupled device (CCD), charge injection devices (CID) and active pixel sensors (APS). Among many optical applications, like earth or space observation, the guidance system in a spacecraft (launcher or satellite) is particularly critical. Then, the reliability of such guidance systems based on image sensors is essential for the space mission. CMOS technology is mainly used in the readout circuit of photonic integrated circuits (ICs). However, CMOS technology is known to be sensitive to single event effects (SEE), such as single event transient (SET) [2]. SETs can be induced by various ionizing particles, i.e., heavy ions, protons, electrons the space radiation environment [3]. SETs can become critical for image devices and ICs boarded in flight because of their critical applications. One of the interests of prediction tools, such as MUSCA SEP3 (MUti-SCAle Single Event Phenomena Prediction Platform) [4-5], is to anticipate the sensitivity trends with the aim to help the designers to select the best layout considering of performances and reliability. Moreover, these investigations lead to reduce the number of testing runs during the qualifications of electronics under high energy particles such as heavy ions. In this work is presented in interest of such approach to understand the failure origins at transistor level with the aim to be able to harden circuits of the readout system of photonic device. This work is focus on infrared (IR) device, designed by Sofradir. Therefore, specificity of cryogenic temperatures, down to 77 K, will be considered, especially in the final paper. These temperatures are used with the aim to reduce the dark current and to increase in performances of the device. **2. SEE prediction tool** MUSCA SEP3 is a SEE prediction tool based on a Monte-Carlo approach which allows a complete simulation from the interaction of the radiation particles with the matter to the occurrence of the soft error in the IC. These simulations uses nuclear database and take into account the dynamic transport and charge collection mechanisms, bipolar amplification, the bias voltage, the layout, and the fabrication process with the aim to build a SET database. The modeling of the Front-End Of Line (FEOL) is based on the description (dimensions and locations) of implants, i.e., drain and source of each n-MOS and p-MOS transistor directly extracted from GDS files. All required layout files and electrical models were provided by Sofradir. Next this SET database is injected on each node at transistor level for an electrical simulation with Spectre simulator with the aim to estimate the soft error response of the circuit. The complete principle of the modeling is reported in previous works [4-5], but all the details of the simulation flow will be presented in the final paper. The comparisons of experimental data and MUSCA SEP3 calculations at 300 K have been performed for 2 designs of DFF used in the readout circuit. Good correlations in terms of LET threshold and SEE saturation of cross section are proposed. More details will be presented and discussed in the final paper. **3. Failure analysis** These failure analyses based on sensitivity mappings can be really useful for designers in order to determine which transistors of the cell are critical and to anticipate design optimizations. In previous work [6], MUSCA SEP3 had already shown the relevance of the estimated critical areas. The simulation results highlight that the transistors of the input of the cell are more sensitive than the transistor of the output of the flip-flop cell. It is interesting to note that even if the global SEE cross section is quite equivalent for the two bias condition of the circuit, i.e., state “1” and state “0” saved in the DFF, the locations of critical areas are strongly different. This point will be illustrated and developed in the final paper. Based on this failure analysis it is possible to propose hardening techniques by design with the aim to reduce the SEE sensitivity of such circuits. This point will be fully illustrated in the final paper. **4. Conclusion and perspectives** This work presents an SEE prediction tool and its interest in failure investigations and in providing a help for designers with the aim to optimize the SEE sensitivity of Sofradir readout circuit. Estimations and a failure analysis at circuit level were presented considering the stored data configuration. Comparisons between predictions and experimental data obtained under heavy ion are consistent. In the final paper, complementary analyses and hardening techniques will be presented **References** [1] G. R. Hopkinson, IEEE Trans. Nucl. Sci., vol. 47, no, 6, pp. 2480-2484, Dec. 2000. [2] C. Virmontois, et al, IEEE Trans. Nucl. Sci., vol. 61, no. 6, pp. 3331-3340, Dec. 2014. [3] D. Falguere, et al, IEEE Trans. Nucl. Sci., vol. 49, no. 6, pp.2782-2887, Dec. 2002. [4] G. Hubert, et al, IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3032-3042, Dec. 2009. [5] G. Hubert, et al, IEEE Trans. Nucl. Sci., vol. 60, no. 6, pp. 4421-4429, Dec. 2013. [6] G. Hubert, et al, IEEE Trans. Nucl. Sci., vol. 61, no. 6, pp. 3178-3186, Dec. 2014.
        Speaker: Mr Laurent Artola (ONERA)
        Paper
        Slides
        summary
      • 11:50
        Single Event Simulation and Error Rate Prediction for Space Electronics in Advanced Semiconductor Technologies 20m
        Abstract: The effect of a single event in today’s advanced semiconductor technology is no longer restricted to a single circuit node, and can depend strongly on layout details, on the angle of the ion, and on the response of the circuit during the charge collection. In order to catch weak spots in circuits and layouts, and to get reliable predictions for space error rates, it is important to have a possibility to model the circuit designs with a full (and correct) description of the layout, of direction of the ion, and of the time profile of the charge collection. This talk discusses simulation techniques which makes this possible, while still being fast enough to be used to generate full cross-section maps and error rate predictions for different radiation environments. Application examples from advanced FinFET technologies (logic) and bulk technologies (including analog and oscillatory circuits) will be presented along with comparisons to measured single event data.
        Speaker: Mr Klas Lilja (Robust Chip)
        Paper
        Slides
    • 12:10 12:30
      Wrap Up
    • 12:30 14:00
      Lunch 1h 30m
    • 14:00 14:15
      ESA DSP Day 2016 Introduction
      Convener: Dr Roland Trautner (ESA/ESTEC)
      • 14:00
        ESA DSP Day 2016 - Day 1 Introduction 15m
        Speaker: Dr Roland Trautner (ESA/ESTEC)
        Slides
    • 14:45 15:45
      Session 1: Rad-Hard DSP Chips
      Convener: Mr Sandi Habinc (Aeroflex Gaisler AB)
      • 14:45
        Scalable Sensor Data Processor: Architecture and Development Status 30m
        Introduction ============ The Scalable Sensor Data Processor (SSDP) is a next generation on-board data processing mixed-signal ASIC, envisaged to be used in future scientific missions requiring high on-board processing capabilities. It offers a novel heterogeneous multicore architecture, combining two high-performance Xentium Digital Signal Processing (DSP) cores [1] together with a general-purpose LEON3FT processor [2], all served by a rich set of Input/Output (I/O) interfaces, including an on-chip Analogue-to-Digital Converter. The SSDP is envisaged to be used in future scientific missions like JUICE [3], easing the development and implementation of data processing functions, without neglecting the capabilities of control offered by the general-purpose processor. The main forces driving its design are processing power, power consumption and radiation tolerance. The focal point of these characteristics lies between flexibility and scalability, enabling the usage of the SSDP in missions with profiles so diverse as deep-space missions or planetary landers. The SSDP development is sustained by a consortium led by Thales Alenia Space España, and comprising Recore Systems, IMEC, Cobham Gaisler and Arquimea, bringing together expertise in the digital, analogue and mixed-signal domains. Such diverse expertise is of the utmost importance in order to tackle the technical challenges posed by integrating the many different components, yet achieving the proposed goals. Architecture ============ The SSDP aims at providing in a single chip all resources needed to perform several tasks pertaining to on-board data processing. Besides the state-of-the-art processing architecture, it has a diverse set of I/O interfaces for data acquisition, supporting external Analogue-to-Digital (ADC) and Digital-to-Analogue (DAC) converters, standardized interfaces like CAN, SPI, SpaceWire (SpW) and GPIO. It supports both high-speed and low-speed on-chip ADCs. These features enable a seamless integration with companion devices and external systems, both current and future. The SSDP architecture can be roughly divided into two major subsystems: Control, embodied by the Cobham Gaisler LEON3FT generic processor and its System-on-a-Chip (SoC) I/O interfaces; and Processing, embodied by Recore Systems Network-on-Chip (NoC) based multicore DSP subsystem, which provides two Xentium DSPs and its associated I/O interfaces. These control and processing subsystems are connected via a Bridge interface, enabling the exchange of data and signalling information between them e.g. interrupts. Despite this abstract subsystem division, the Control subsystem can also be used for processing tasks, thus exploiting the processing power of the LEON3FT processor and its I/O interfaces. Likewise, the Processing subsystem can be used to command interfaces on the Controlling subsystem. The ability of scaling the system was not neglected, and a Parallel Interface for chip-to-chip communication is included. This interface allows interconnection an SSDP to either another SSDP, an FPGA or other suitable device. This interconnection enables parallel data exchange with data-rates up to 800 Mbps, and includes flow-control mechanisms to ensure efficient communication. Control Subsystem ----------------- The control subsystem has a LEON3FT at its heart, supported by EEPROM and SRAM for application storage and execution. This is further enriched by typical I/O interfaces, such as SpW, CAN, UART, GPIO, SPI, and others. The SSDP Fault-Tolerant Memory Controller will support the emerging MRAM technology, which can be used instead of current EEPROM technologies. Time-keeping will be managed by the novel SpaceWire Time Distribution Protocol (SpW-TDP) [4], whose IP core will be enhanced to meet the SSDP time management requirements. The architecture of the Control system is intended to be highly compatible with the commercially available GR712 processor from Cobham Gaisler, thus enabling the reuse in the SSDP of code, tools and procedures already developed for the GR712. Processing Subsystem -------------------- The processing subsystem is powered by Recore Systems multicore DSP subsystem IP, which provides two Xentium DSPs, connected to local memories and peripherals via a highly performing NoC. The NoC has a 32-bit width, and it will work at system speed, thus yielding a maximum bidirectional throughput of 3.2 Gigabit per second. The storage of (volatile) data is performed through a rich hierarchy of memories, ranging from local high-speed tightly-coupled memories to external SDRAM at 100 MHz. Data acquisition can be performed via an external ADC, or using the on-chip fast ADC which supports sample rates between 20 Msps and 100 Msps. The configuration and exploitation of external ADC and DAC components will be possible from the Processing Subsystem, with sample rates up to 50 Mega-samples per second. Such devices can be configured via a serial bus like SPI or I2C. Development Status ================== The SSDP consortium encompasses several partners, with different domains of expertise: Recore Systems, providing the multicore DSP subsystem; IMEC, providing layout services, specific IP cores and the DARE cell library; Cobham Gaisler, with the LEON3FT subsystem; and Arquimea, with the on-chip fast ADC. The SSDP development will result in a CQFP mixed-signal ASIC, built in 180 nm DARE digital cell technology [5]. Engineering Models (EMs), Flight Models (FMs) and evaluation boards will be commercialized by Cobham Gaisler. The SRR was successfully closed out in October 2015, and the development is entering now its prototyping and validation stage, which will culminate with a PDR. For that, a prototyping board based on a Xilinx Kintex Ultrascale FPGA is being developed, which will provide enough FPGA resources to embed in a single chip both subsystems. This board will provide all the I/O interfaces needed by the SSDP, thus allowing their validation. The SSDP validation activities will be carried out with the help of a National Intruments PXI testbench comprising both hardware and LabView software. The SSDP will run software to support the validation procedures. Such a setup allows a simple yet powerful validation loop, which can be used at all levels of the validation procedures. References ================== [1] Recore Systems, Xentium® VLIW DSP IP Core - Product Brief, 2012. [2] Cobham Gaisler, GRLIB IP Core User's Manual, 2016. [3] European Space Agency, “JUICE Definition Study Report”, 2014. [4] Cobham Gaisler, “High Accuracy Time Synchronization over SpaceWire Networks”, 2013. [5] S. Redant, R. Marec, L. Baguena, E. Liegeon, J. Soucarre, B. Van Thielen, G. Beeckman, P. Ribeiro, A. Fernandez-Leon and B. Glass, “The Design Against Radiation Effects (DARE) Library,” in 5th Radiation Effects on Components and Systems Workshop (RADECS), Madrid, 2004.
        Speaker: Mr Ricardo Pinto (Thales Alenia Space)
        Paper
        Slides
        summary
      • 15:15
        RC64: High Performance Rad-Hard Manycore DSP 30m
        The RC64 project has been inspired by ESA NG-DSP roadmap and by plans of European space industry. In addition to very high performance DSP capabilities, RC64 offers ESA-supported SpaceFibre links, interfaces to European space-qualified ADC and DAC, and a variety of other peripherals useful in European on-board DSP. RC64 is supported by three European FP7/Horizon2020 projects (QI2S—real time material identification on RC64, MacSpace—signal processing on RC64, and S3NET—formation flight of multiple small satellites) in consortia with several European companies and academia. RC64 will be ITAR-free. RC64 is designed as a rad-hard high-performance many-core signal processor comprising 64 CEVA X1643 DSP cores, 4 MBytes on-chip shared memory, telecomm FEC accelerators for DVB-S2X/RCS2 modems and high bandwidth I/O. Two packaging options will be offered, a hermetically sealed CCGA-624 (addressing ESCC9000 qualification) and a PBGA-624. It is designed for a variety of space applications. RC64 includes twelve SpaceFibre integrated full duplex high speed serial links (HSSL) using 6.25Gbps SERDES interfaces on chip, for a combined data rate of up to 120 Gbps. Four links also double as SRIO. The HSSLs enable efficient connectivity among multiple RC64 chips as well as FPGAs, ASICs and future ADC and DAC. DDR2/3 SDRAM interfaces include Reed-Solomon ECC to protect from SDRAM SEFI and SEE. The 32+16 bit wide DDR2/3 interface supports up to 25Gbps throughput. Other I/O interfaces in RC64 include two SpaceWire for control and four for instrument data, parallel LVDS interfaces for ADC and DAC connectivity, and ECC-protected interface to ten 8-bit flash memories. The on-chip shared memory system of RC64 complements the write-through data cache, the instruction cache, and the private store of each core. To support the unique task-oriented programming (TOP) model, the 64 cores access the single shared memory through the 64-by-256 ports high-throughput, low-latency multistage interconnection network, enabling simultaneous access of all processors to the shared memory with very little conflicts. Thanks to the caches, access to shared memory happens either for fetching a complete cache line (the interfaces and the interconnection network are optimized for transferring complete cache lines rather than individual words) or for writing a single word, due to the write-through mechanism. While write-through may result in higher traffic rate to memory than write-back, it eliminates the need for complex inter-core cache coordination mechanisms such as snooping, locking, coherency checking and directories. Instead, the programming model minimizes memory conflicts and prevents software from relying on shared memory synchronization. The on-chip 4 MByte shared memory acts as a local-store memory. Access to off-chip DDR2/3 memory is facilitated by software-controlled DMA. This approach simplifies software development and it is found to be very useful for DSP applications, which favor streaming over cache-based access to memory. Most DSP applications are implemented without resorting to external DDR memory at all. A hardware scheduler assigns tasks to processors. Each processor executes its task from its cache storage, accessing shared memory only when needed. When task execution is completed, the processor notifies the scheduler, which can subsequently assign a new task to that processor. RC64 can operate on its own, booting its code from a flash device. It is better utilized with an attached control processor, such as the dual-core LEON GR712RC, which controls RC64 via SpW RMAP ports. A single external processor may control multiple RC64 chips, chained via a SpW ring. RC64 contains several FDIR capabilities, such as tracing, error monitoring and full access to internal state. The control processor has full access to RC64 and its FDIR features. No operating system is used on RC64. A run-time executive manages boot and FDIR, handles all DMA-based I/O, supports task start/stop and task control by the hardware scheduler, handles all error detection and correction, communicates with the control processor, and provides networking to other RC64 chips and other devices. For instance, the run-time executive performs the following sequence of actions upon input of a data item: (1) the DMA controller is programmed to receive a block of data from input and store it into shared memory, (2) the DMA controller issues an interrupt, (3) an interrupt handling routine is preemptively invoked on one of the cores (4) the interrupt handling routine enqueues a descriptor (containing a pointer to the received data block) into an input control queue and generates a signal (called “software event”) for the scheduler, (5) the hardware scheduler, triggered by that signal, enables a task waiting for that data and enqueues it into the queue of tasks that are ready for execution, (6) eventually, the hardware scheduler dispatches that task to some processor, (7) the task dequeues the descriptor from the input control queue and consumes the data. The PRAM-like programming model of RC64 is based on non-preemptive execution of multiple sequential tasks. The programmer defines the tasks in sequential C code, and defines their dependencies and priorities in a (directed) task graph. Tasks are executed by cores and the task graph is ‘executed’ by the hardware scheduler. In this shared-memory model, concurrent tasks do not communicate. Concurrent tasks may share read-only data but they cannot share data that is written by any one of them. Execution of concurrent tasks does not necessarily happen at the same time—they may execute together or at any order, as determined by the scheduler. Some tasks, typically amenable to independent data parallelism, may be duplicable, accompanied by a quota that determines the number of instances that should be executed. All instances of the same duplicable task are mutually independent (they do not write-share any data) and concurrent. These instances are distinguishable from each other by their instance number. Ideally, their execution time is short (fine granularity). Special pipeline techniques are available for multi-stage signal processing of streams of continuous data, assuring very high core utilization and processing that employ the on-chip shared memory and avoid time-consuming access to external DDR memory. A set of tools is being developed to help write software for RC64. The tool chain encompasses CEVA tools for the individual core (compiler, assembler, linker and a set of DSP libraries) and contains the following enhancements for manycore programming and for RC64: A task compiler (converting task graphs to scheduler tables), a manycore emulator (for developing parallel applications on standard workstations), manycore cycle-accurate simulator and debugger, a tracer and event recorder, a parallel program profiler, and a set of parallel DSP libraries. When a single RC64 is not sufficiently powerful for the application, multiple RC64 chips can be joined together. The multiple RC64 chips are interconnected with high-speed serial links using SpaceFibre. A networking software layer in the run-time executive facilitates easy and virtualized communications among the many chips. RC64 has been designed for integration with tens or hundreds of other RC64 chips, enabling very powerful digital signal processing in space. RC64 will be implemented on 65nm CMOS. It will dissipate a maximum of 10W, when all 64 DSP cores are active at 300 MHz and all 12 SpaceFibre links are transmitting. Power is reduced proportionately to the number of active cores, active outputs and clock frequency. RC64 is designed for operation at 300 MHz and will achieve 38 GFLOPS (single precision) and 76 GMAC (16-bit). The 12 high speed serial links offer a total bandwidth of 120 Gbps. Additional high bandwidth is enabled for memories (25 Gbps DDR3 interface of 32 bit at 800 Mword/s with additional 16 bits for ECC) and for high performance ADC and DAC (38 Gbps over 48 LVDS channels of 800 Mbps). RC64 is implemented using RadSafe™ rad-hard-by-design (RHBD) technology and library. RadSafe™ is designed for a wide range of space missions, enabling TID tolerance to 300 kRad(Si), no latchup and very low SEU rate. All memories on chip are protected by various means and varying levels of error correction and detection. Special protection is designed for registers that hold data for extended time, such as configuration registers. RC64 implements extensive means for fault detection, isolation and recovery (FDIR). An external host can reset, boot and scrub the device through dual RMAP SpaceWire ports. RC64 contains numerous error counters and monitors that collect and report error statistics. Trace buffers, allocated in shared memory as desired, enable rollback and analysis (in addition to helping debug). Faulty sub-systems may be shut down and the scheduler is designed to operate with partial configurations. ![abstract with figures][1] [1]: http://www.ramon-chips.com/papers/RC64HighPerformanceRadHardManycoreDSPDay2016.pdf
        Speaker: Prof. Ran Ginosar (Ramon Chips)
        Paper
        Slides
        summary
    • 15:45 16:00
      Coffee break
    • 16:00 17:00
      Session 2: Test, Verification and Qualification of DSP Chips
      Convener: Mr Boris Glass (ESA)
      • 16:00
        ESCC Qualification of Space Components - Schemes and New Opportunities 30m
        The European Space Components Coordination (ESCC) system has been developed exclusively to support the procurement and space qualification of EEE Components. It is a unique system in that the requirements are not only dictated by end-users, agencies or industry, but are compiled and agreed by manufacturers, component users and qualifying agencies working together in a shared standardization effort. The system is unique as well in maintaining a methodology for Quality Assurance which in fact supports the customers' high level of trust and offers them a reduced cost of ownership - as quality problems are very infrequent with ESCC components. ESCC qualified components are acceptable for use in all ESA satellite missions and meet as well the requirements of most commercial and scientific space missions. Various schemes of qualification co-exist in the ESCC system, and all have been used over the years to achieve qualification of microelectronics products and manufacturer's technology flows and capability domains. This presentation aims at explaining the main differences in qualification schemes and to describe in the simplest possible way the steps that lead to ESCC qualification. The roles and responsibilities of component manufacturer and involved agencies shall be explained. In addition, it may be noted that several standardization initiatives have been developing and running , since some years ago, to build alternative certification schemes in order to address fragmented supply chains. This was reported already at AMICSA in 2012. The presentation in 2016 will show the progress achieved and the status of additional activities related to the same topic. The ESCC system is supported by some 600+ published specifications. The design of this system of specifications is not as user-friendly as desirable. The presentation will try to offer some helicopter-view of these specifications and their interrelations. The intention is to offer a guide through the system of specifications so that one knows what is a good starting point when approaching the system for the first time, and which parts of it are really mandatory reading to understand it all well. The ESCC system is based as well on the technical collaboration among its partners (manufacturers, users, agencies). This cooperation is effective in addressing technology harmonization and the development of standards. The presentation will explain these common efforts in some detail and offer links and contact details to those who may want to know more. In addition to qualification and specifications, ESCC has another visible output, which is the European Preferred Parts List (EPPL). The presentation will address what the EPPL is and how it works, and how it is related to the ESA applicable standards for space components. Finally, the eventual introduction of a new qualification methodology, currently in discussion within the ESCC community, may be reported at this occasion- but only if it has reached a minimum internal level of maturity (the first 'go-ahead' to develop such approach could be achieved already in May 2016).
        Speaker: Mr Fernando Martinez (ESA)
        Paper
        Slides
        summary
      • 16:30
        Scalable Sensor Data Processor: Testing and Validation 30m
        SSDP Architecture ================= The Scalable Sensor Data Processor (SSDP) is a heterogeneous multicore architecture for high-performance on-board data processing. Broadly, it embeds a Control block based on the well-known Cobham Gaisler LEON3 System-on-a-Chip (SoC) [1], with a LEON3FT general-purpose processor connected to several I/O interfaces via AMBA bus. The Processing block is based on Recore Systems multicore Digital Signal Processor (DSP) IP [2], containing two Xentium DSPs, connected to I/O interfaces and SDRAM memory via a Network-on-Chip (NoC). These blocks are connected via a bidirectional bridge, translating signalling and data transfers between block domains. The Control block provides several I/O interfaces, like SpaceWire (SpW), CAN, GPIO, SPI and I2C, among others. The Processing block has I/O interfaces more oriented towards data exchange and data conversion, with SpW interfaces for networked I/O and ADC/DAC interfacing with data conversion devices. Furthermore, the ADC/DAC interfaces can also be used as a high-throughput Parallel Interface for chip-to-chip communication. This interface possesses flow-control mechanisms, and can achieve a maximum throughput of 800 Mbps. Prototyping Support =================== The SSDP ASIC presents several challenges from a prototyping perspective: amount and quality of FPGA resources in order to accommodate all the logic needed by the control and processing blocks with reasonable performance; existence of mixed-signal (analogue and digital, e.g. ADCs) Intellectual Property (IP) blocks which may/can not be modelled nor prototyped. The SSDP ASIC design is being prototyped in a state-of-the-art Xilinx Kintex Ultrascale XCKU060 FPGA [3], mounted on a custom board designed in-house at TASE, named SSDP-PROB (SSDP Prototyping Board). This board provides all the needed I/O interfaces, together with SDRAM memory support. Mezzanine connectors have also been added in order to allow expanding the prototyping and validation activities, thus opening the possibility to either add more components, e.g. ADC and/or DAC devices, or probe internal FPGA signals directly. Testing and Validation ====================== Testing and validation is usually performed by providing the Unit Under Test (UUT) with stimuli, and then observe the outputs, whose correctness is assessed by comparison with a reference model. Applying this methodology to the SSDP requires the provision of Electrical Ground Support Equipment (EGSE), in order to provide the necessary stimuli (I/O activities), and capture the outputs for verification. The verification of output correctness is based either on specifications of I/O interfaces, or application output based on reference models. Setup ----- The test setup for SSDP requires an integrated and flexible EGSE platform, given the diversity of I/O interfaces. Such a platform is embodied by the National Instruments (NI) PXI product line [4], which offers the possibility to embed in a single chassis the controller cards and I/O interfaces. Such a platform is controlled with LabView, an industry standard software w.r.t. testing design and execution, and the testing activities can be modelled as LabView applications All the I/O interfaces of interest present on the board are connected to the test bench, using adequate EGSE I/O cards. Furthermore, an FPGA-based digital I/O module was used in order to control the SSDP, and at the same time offer the possibility to embed some of the testing activities directly into hardware. The EGSE interacts with the software layer on the SSDP via a set of pre-defined tele-commands (TCs). The TCs can be used to perform the following actions on the SSDP: setup interfaces; initialize memory areas and patterns; start and stop tests. Methodology ----------- SSDP testing activities can be divided in three classes, with increasing abstraction levels: **interface testing**, where one or more interfaces are tested, in order to assess their status of compliance to the (individual) specifications; **benchmark testing**, where an application is used to assess the performance of a given system or subsystem; **validation testing**, where an application is used to validate the overall system. In the case of **interface testing**, the philosophy followed is to delegate the testing activities almost solely to the EGSE, and add a minimal amount of software support to the SSDP in order to support the testing activities (drivers). The main advantage of this philosophy is to concentrate the bulk of test design and implementation on the EGSE application, thus easing the task of test design and execution. In **benchmark testing**, an application is executed and the time it takes to complete is evaluated. The results can be used to assess the performance of the tested system, and even compare it with others systems. An example of a benchmark is the amount of time needed to perform a give operation on a set of data, e.g. the FFT on a set of 1024 points of data. In the SSDP scope, the set of benchmarks defined for the NGDSP [5] will be used, in order to assess the performance figures of the processing block. Regarding **validation testing**, an application is executed in the SSDP, e.g., filtering, with the EGSE emulating the application’s expected environment, e.g. data acquisition from a sensor or data storage in a mass memory. The resulting output is then verified to be compliant with a reference model, e.g. output of the same application in a modelling tool like Matlab. Status ====== The testing and validation activities on the SSDP are currently at the interface testing level, with tests being developed for each I/O interface. These activities involve the development of specific software pieces in order to support the testing activities. The benchmark testing is envisaged to follow the NGDSP benchmark, making use of a normalized mark and enabling the comparison with other architectures. The results can also be used to make improvements to the architecture of the SSDP, or identify potential bottlenecks. The validation testing is envisaged to use the PXI EGSE as an emulator, providing stimuli and capture outputs to an application running on the SSDP. Envisaged applications include several representative use-cases, such as filtering, down-sampling or compression for the processing part, and sensor & actuator interface for the control part, via emulation. References ========== [1] Cobham Gaisler, GRLIB IP Core User's Manual, 2016. [2] Recore Systems, Xentium® VLIW DSP IP Core - Product Brief, 2012. [3] Xilinx Inc., UltraScale Architecture and Product Overview, 2016. [4] National Instruments, “PXI: The Industry Standard Platform for Instrumentation”, 2014. [5] TEC-EDP/2008.18/RT, “Next Generation Space Digital Signal Processor Software Benchmark”, ESA, 2008.
        Speaker: Mr Ricardo Pinto (Thales Alenia Space)
        Paper
        Slides
        summary
    • 17:00 18:00
      Session 3: COTS based DSP Systems and Boards
      Convener: Dr Roland Trautner (ESA/ESTEC)
      • 17:00
        High Performance COTS based Computer for Regenerative Telecom Payloads 30m
        The use of COTS based computers for high performance digital processing in space application is an alternative to fully space-grade systems. Indeed, state of the art commercial processing devices achieve significantly higher performance than space-grade devices but generally do not fulfil space mission’s expectations mainly in term of radiation tolerance and thermal dissipation. However, within a system surrounded by space-grade devices and software for monitoring and control, such devices may deliver extreme processing performance with an overall level of reliability and availability which is fully acceptable for a given mission. Within the framework of ESA TRP/GSTP studies devoted to the development of High Performance COTS Based Computers (HiP-CBC) in space applications, a generic architecture has been defined by Airbus Defence and Space to efficiently mitigate the erratic behaviour of commercial grade processing devices such as DSPs, general purpose micro-processors or FPGAs when they are submitted to the space radiation environment. Functions for detection and management of the sporadic errors induced by the radiation effects are developed with standard space-grade device - called SmartIO - interfacing with one or several high performance data processing boards implemented with commercial processing devices. A TRL 5/6 prototype implementation with a SmartIO based on a SCOC3 component (SCOC3 is a Spacecraft Controller on a Chip including a LEON3 processor with several interfaces such as 1553, CAN bus, and SpaceWire) and COTS based processing board made around Texas Instrument TMS320C6727 DSPs has been designed and manufactured within the frame of this ESA project. This demonstrator has validated the concept and the maturity of the so called Generation 1 of SmartIO (i.e. based on fully mature 2015 existing technologies) which remains limited to the coverage of applications with moderate needs in term of data processing due to the limited bandwidth of SpaceWire (~200 Mbps) and processing performance of the SCOC3 (80 MIPS). Higher rates will be required for e.g. on-board image, radar or telecom signal processing with a support of serial links in the 1-10 Gbps range such as Serial RapidIO or the SpaceFibre currently in development. For example, Machine-to-Machine (M2M) communications, serving the broader Internet-of-Things (IoT), are receiving increasing interest. They have a very large market and growth potential, with increasing needs in the low-cost, low data rate segment. Complementing the ground networking through satellites is the only solution to provide global continuous coverage, with growing interest in low altitude satellite constellations embarking Software Defined Radio (SDR) payloads. However, current space technologies are not adequate to offer a competitive solution for commercial services with a satisfactory level of quality of service. To be commercially successful, flexible and regenerative payloads, delivering very high performances under severe cost, size, and energy constraints are mandatory. This is where the HiP-CBC concept and its SmartIO comes in; “enabling access” to the processing performances of latest COTS components based on more power efficient silicon technologies, which is identified as the most promising strategy. Many other applications related for instance to data collection, spectrum survey or air-traffic control could benefit of such development. Exploring this promising technical path, Airbus Defence and Space is currently working on an innovative architecture of a generic Radio-Digital Processing Module (R-DSP) based on COTS components with the Generation 2 of the SmartIO with support of ESA through an ARTES program. For that purpose, commercial SRAM FPGAs have been selected to implement the high processing layer of the R-DSP, able to deliver a theoretical capacity of at least 50 GMAC/s to fulfil various mission needs. The implementation of the SmartIO function has been extended to a rad-hard anti-fuse FPGA, which provides a sufficient number of I/O pins and bandwidth capacity to interconnect a multi-port RF front-end with several mitigated commercial FPGAs. A SpaceWire link is also included in the design to provide a standard interface between the SmartIO and the rest of the payload network. The resulting architecture is modular and can be easily adapted to implement Triple Modular Redundancy (TMR) or Dual Modular Redundancy (DMR) macro-mitigation techniques, according to the availability requirements of the target mission.
        Speaker: Mr Olivier NOTEBAERT (Airbus Defence and Space)
        Paper
        Slides
        summary
      • 17:30
        SpaceWire and SpaceFibre Interconnect for High Performance DSPs 30m
        STAR-Dundee with the University of Dundee has recently designed several high performance DSP units each using SpaceWire or SpaceFibre interfaces to provide an input/output performance in-line with the capabilities of the specific DSP processor. The first DSP unit is for the High Processing Power Digital Signal Processor (HPPDSP) project, which is an ESA funded project led by AirbusDS with STAR-Dundee Ltd and CG Space. It aims to build a high performance, programmable DSP processor suitable for spaceflight applications. STAR-Dundee was responsible for the hardware, FPGA and low level software development. The HPPDSP is designed around the TI TMS320C6727B processor which is available as a space qualified part. The DSP processor connects to external SDRAM via its EMIF (external memory interface) bus. Peripherals that are directly controlled by the DSP processor are attached to the EMIF bus via an FPGA. Other peripherals that are able to access DSP memory and registers in parallel with the DSP processor are attached to the UHPI (Universal Host Processor Interface) bus of the DSP processor via the FPGA. A board has been designed incorporating the TMS320C6727 processor, SDRAM memory and a Xilinx Virtex 4 FPGA. The FPGA includes EDAC for the SDRAM memory, memory management, SpaceFibre and SpaceWire interfaces, and other general purpose interfaces. A high sample rate ADC/DAC interface is also included. The second DSP project is a high performance FFT processor for a THz Radiometer. Implemented in various FPGA technologies this Wideband Spectrometer (WBS) is able to perform 2k point complex FFTs at a sample rate of around 2.4 Gsamples/s in radiation tolerant technology, a total processing power of more than 200 GOPS. Each FFT board processes a 2 GHz wide band to a resolution of around 3 MHz. SpaceWire is used to gather the data from several of these spectrum analysers to handle up to 12 GHz bandwidth. The third DSP project is the Ramon Chips RC64 Many Core DSP processor, where STAR-Dundee provided the SpaceWire and SpaceFibre technology for this very powerful programmable DSP processor. The paper will describe the HPPDSP architecture, the FPGA design and the board design. It will give an overview of the WBS system and present the latest implementation of this high performance DSP system. A brief summary of the RC64 processor will be provided. In each case the role of SpaceWire and SpaceFibre in the different systems will be described.
        Speaker: Prof. Steve Parkes (University of Dundee)
        Paper
        Slides
        summary
    • 18:00 18:15
      ESA DSP Day - Day 1 Oral Sessions Wrap-up and Poster Session Introduction / Day 2 Logistics
    • 18:15 19:30
      Session 4: DSP Day Reception and Poster Session
      • 18:15
        Characterization and qualification of microcontrollers and DSPs in extreme temperatures 1h 15m
        **1.Introduction** Microcontrollers and DSPs are key components of embedded systems for most applications (space, avionics, industry…). The reliability of these components has to be asserted to ensure the correct working of the system for the duration of its mission while preserving its performances. Designers are currently greatly tempted to use commercial components for their applications; they are easier to use and buy while providing higher calculation performances. However, these components generally have not been tested in extreme environments. From these facts, it seems mandatory to consider the importance of testing microcontrollers and DSPs before employing them in space applications, or any other application that comes with an extreme environment. That is the reason why the electrical test and reliability team of THALES Communications & Security worked on the subject. This document summarizes test methods and shows some results in regards to testing and qualification of microcontrollers and DSPs in high temperatures. Results described in this abstract have been observed by testing ARM M0 & M4 microcontrollers for industrial application. **2.Characterization** Characterization tests were performed on a few components to quantify the drift of their performance and behavior relatively to temperature. In order to obtain the most precise measurements, the part under test is mounted on a daughter board plugged into an ATE (Automatic Test Equipment). High temperature environment is achieved using an air stream temperature forcing system (see picture below). http://hpics.li/c5ac942 *Figure 1: Mutest ATE with ThermoStream to characterize components* A firmware including several test scenarios is programmed into the device. The ATE then orders the component to launch perform the various test scenarios with voltage, clock frequency, and temperature variations. More exactly, the following parameters can be tested: - Core functionalities (boot sequence, multi-core communication, voltage supervisor, interruption) - Clock structure (internal clocks, external clocks, PLL, timers) · Processing modules (ALU, FPU, TMU) - Internal memory (volatile and nonvolatile, user and program memory) - Peripheral communication modules (ex: UART, SPI, I2C, CAN, Ethernet) - Analog blocks (ADC, DAC, comparator, PWM) - Operating and low power consumption modes - I/O characteristics (leakage current, input and output voltage) According to the tested device, various parameters evolve over temperature, the most noticeable one being current consumption (see the chart below): http://hpics.li/d95d930 *Figure 2: Current consumption of tested microcontroller in low power mode over temperature* This first chart shows the current consumption of a microcontroller in a low power mode according to voltage (2.5 or 3.3V) setting and temperature. The low power mode displays an obvious temperature limit to its use. Indeed, from 210°C @2.5V and 215°C @3.3V current consumption is the same as in normal mode. This result also highlights the need for a higher voltage supply to function as temperature increases. Nevertheless, a different test performed on another component, points out the decrease of the maximal operating voltage supply as temperature increases. The root cause of this would be the decrease of the output voltage provided by the internal regulator when current consumption gets too high (higher current consumption as temperature increases). The application report “Understanding the Terms and Definitions of LDO Voltage” [2] mentions this particular behavior relative to voltage regulators. http://hpics.li/e113d3a *Figure 3: Regulator output voltage vs output current draw* This phenomenon can be observed when testing the ADC module by measuring a stable input (VCC/2) while using the internal voltage regulator as voltage reference. http://hpics.li/3e86bfb *Figure 4: ADC measurements with internal reference* On the other hand, performing the same test with an external reference gives stable result up to at least 190°C. In the case of the internal reference, the ADC output code positive data at high temperature comes from a negative drift of the voltage reference. What’s more, the higher the voltage supply, the higher the ADC code gets. It goes without saying that these examples are only a few among other parameters to show both functional and parametric behavior changes along with temperature. **3.Qualification** Assessing the functional configurations of the device under test is one thing, ascertaining its ability to remain in working conditions for the duration of its application is yet another. As for the characterization, several scenarios are implemented into the embedded firmware. A digital sequencer in the cold side continuously and sequentially calls all scenarios executed by devices under test in the hot side. http://hpics.li/88459a7 *Figure 5: SANSA architecture* This homemade system is named SANSA: Solution to Activate Numerical Systems for Ageing. Its aim is to simulate as well as possible the working conditions of the device under test (extreme environment for thousands of hours). Such a testing methodology quantifies drifts over time of both parametric and functional performances of the tested parts. A critical parameter to monitor during such an ageing test is the complete retention of the program memory embedded in the DSP. Data corruption might reach error rat that cannot be compensated by correction algorithms (ECC). The JEDEC standard JESD218 [3] states the decrease in retention time capabilities of a typical FLASH memory in regards to temperature by using models from the JEDEC standard JEP122G [4]. For example, the Arrhenius equation can be used to compute the acceleration factor due to a temperature increase, and to have an estimation of the retention degradation caused by temperature. **4.Conclusion** This document summarizes test methods to ensure performance and reliability of a microcontroller or a DSP in high temperatures, and shows some test results. In addition, this methodology can also be applied to test devices’ behaviors in a radiation environment, especially to test internal memory resiliency. To finish, this qualification process can just as well be implemented to qualify FPGA devices for space applications, and to compare their performances with DSPs’. **Reference** *[1] “Extreme Environment Electronics”, John D. Cressler, Alan Mantooth* *[2] “SLVA079: Understanding the Terms and Definitions of LDO Voltage Regulators”, Bang S. Lee, Texas Instrument* *[3] “JEDEC standard JESD218: Solid-State Drive (SSD) Requirements and Endurance Test Method”* *[4] “JEDEC standard JEP122G: Failure Mechanisms and Models for Semiconductor Devices”*
        Speaker: Mr Flavien DOZOLME (THALES Communications & Security)
      • 18:15
        DVB-S2 Software Defined Radio Modem on the RC64 Manycore DSP 1h 15m
        RC64 is designed as a high performance rad-hard manycore DSP processor for space applications. Software Defined Radio (SDR) and modems constitute very demanding applications. This paper investigates the implementation of DVB-S2/DVB-S2x modems on RC64. An LDPC hardware accelerator is included in RC64 to support efficient modems, and as a result RC64 achieves in excess of 2 Gbps transmit rate and 1 Gbps receive rate. The RC64 DVB-S2 modem has been developed using a multi-level methodology and simulators. The paper presents the simulator, the modem algorithms, implementation details, parallel programming of the model, and performance evaluation. The RC64 DVB-S2 simulator includes a data generator that creates baseband frames. A transmitter encodes and modulates the frames according to DVB-S2 and DVB-S2X standards. A channel simulator adds noise and impairments. A receiver demodulates and decodes the signal, and an analyzer compares the sent and received signals. The simulator enables testing and performance optimization regarding modem quality (bit error rate for a range of channel impairments, signal to noise ratio and bandwidth), modem bitrate (performance of RC64 executing the modem application), bottleneck analysis (identify required accelerator(s) for the modem) and hardware accelerators type and capacity (validation before hardware integration). Modem development is carried out through six levels of refinement. Algorithm development starts by coding in Matlab a high level model of the modem, and proceeds through stages until finally parallel C code is employed to program the actual RC64. We start with an unrestricted algorithm, implemented in Matlab (level 1). The accelerators code is replaced by a Matlab executable (mex) file generated from RTL descriptions of the accelerators. Level 1 serves as golden model, to which subsequent level models may be compared. Level 2 takes into account architectural restrictions of RC64 such as limited memory and real-time constraints. For instance, receiver input samples are processed in pre-defined sample groups rather than in frame size sample groups. In the third level, Matlab floating-point computations are replaced by Matlab fixed point at a word precision of 16 bits, compatible with high-speed arithmetic on the DSP cores of RC64. Accelerator models are replaced by more precise ones driven from RTL. Outputs are carefully compared with the results of the floating-point models, to assure minimal signal degradation. At level 4, Matlab is replaced by code in the C language, compatible with the compiler for the DSP cores in RC64. The Matlab simulator models of the transmitter and receiver are replaced by models for the cycle accurate simulator of RC64. The output must be exactly the same as produced in level 3. The accelerator code is a function in C representing the hardware accelerator. At level 5, the code is parallelized to execute on RC64 and further optimizations are performed to take advantage of specific hardware features of the DSP cores. The accelerators function is executed as a separate task, in parallel with other tasks. In level 6 the entire modem is executed on RC64 hardware.
        Speaker: Prof. Ran Ginosar (Ramon Chips)
        Paper
        summary
      • 18:15
        Open-Source Instrument Flight Software for CHEOPS 1h 15m
        The Department of Astrophysics at the University of Vienna is a provider of payload instrument flight software (IFSW) with a focus on the compression of the instrument science data. One of the projects under development is the instrument flight software for the first ESA-S class mission CHEOPS (CHaracterising ExOPlanet Satellite). CHEOPS is being built for launch in late 2017 to provide ultra-high precision photometry measurements of transits of known exo-planets. It carries only a single optical instrument, which is equipped with a data processing unit that runs the IFSW to carry out various ECSS-Service oriented control and highly tailored data processing tasks. This software is developed at the University of Vienna as an open-source software, this includes all drivers and modules the flight software is composed of, but also the EGSE (Electronic Ground Support Equipment) software and the simulators used for the development. This means, that everybody is free to use the sources of the full application or of interesting components, modify and redistribute them according to the GPLv2 license. We will take a look at the architectural design of the software, focusing on parts that may be useful for other projects. The Data Processing Unit (DPU) hardware of CHEOPS is built by the Institute for Space Research, IWF Graz. As processor, the GR712RC dual-core Leon3 was chosen, mainly because it already includes a Milbus (MIL-STD-1553) core, which is needed for the communication with the spacecraft (AS-250 platform). Internally, SpaceWire is used to communicate with the camera detector unit. The DPU is equipped with 64 MiB SRAM and a 16 GB FLASH memory. The two cores are used in Asymmetric Multi-Processing (AMP) style, but only a single shared executable is run. When looking hierarchically at the IFSW, it is composed of three layers, a basic software, an ECSS services-providing framework and the high level application software. The Instrument Basic Software (IBSW) provides access to the hardware. Drivers for the SpaceWire (GRSPW2) cores and the Milbus core (Microsemi) were developed from scratch. Multi-threading is provided by the FSU pthreads implementation that comes with the compiler runtime library (BCC 4.4.2). The CPU is set up to run all the system-specific tasks (communication, control) on the first core and the science data processing as a single thread on the second core. All threads are encapsulated in real-time containers and synchronization is achieved using the ceiling priority protocol for shared resources and the single-producer single-consumer methodology whenever possible. The basic software handles high-precision timing, FLASH memory access and the EDAC handler in separate threads. On top of the basic software the CORDET service framework is implemented. This software library is developed and provided as open-source software by PnP Software, Tägerwilen (CH). It provides a generic software infrastructure for PUS-based applications, a consistent solution for the communication and control services, event handling and FDIR procedures. The framework is attached to the basic software via call-back functions. Similar to the basic software, the framework library only adds few KiB in size to the application. On the highest level of the application are the science data processing tasks. The main task of the IFSW is to process the optical CCD images of the detector unit and compress them in real-time. This task is achieved by a highly tailored, yet configurable data processing chain. It starts with pre-processing tasks, such as the non-linearity correction of the pixel fluxes. Lossy operations are the image stacking, the selection of the science window from the full CCD area and an additional quantisation step to deal with the high read-noise in high-gain settings. The reduced data are compressed using e.g. 2D wavelet transforms and arithmetic compression with a semi-adaptive model. Several components of this are re-used from the HERSCHEL/PACS data compression software. Another interesting task of the application software is the provision of precise position measurements to the spacecraft in a closed loop. As the thermal stress on the telescope structure causes misalignment of the instrument with the star trackers, centroid measurements have to be provided to the platform. A set of algorithms has been developed and analyzed in depth with a wide range of applications in mind. This misalignment is also an issue for the initial pointing, thus the IFSW provides target recognition algorithms to enable the identification of the correct star and to move it to the desired location on the CCD. Three algorithms were developed for this purpose, which will be used in different observation conditions. As a lesson learnt from previous projects, the IFSW is structured and developed in a way that the actual software and the simulator software for the PC are generated simultaneously from the same code. The main difference is that the PC compilation uses POSIX sockets instead of the actual hardware interfaces. Such hardware can be used through simple routing applications, which connect to the sockets. That way the PC simulators can be connected either directly to each other, or to the target hardware under test and provide thus the most flexible test environment that can be envisioned. Following our open-source strategy, we have also developed a central checkout system application from scratch. This application runs the test control scripts in Python and it uses the instrument database to encode and decode all TM/TC. As it is built in Python, a large amount of analysis methods are available. We will present the flight software and the related components to provide help for developers that are interested to re-use parts of the open-source software and thus facilitate their work.
        Speaker: Dr Roland Ottensamer (University of Vienna)
      • 18:15
        Radiation Intelligent Memory Controller IP Core 1h 15m
        I. INTRODUCTION DDR2 SDRAM is a very attractive technology for space application thanks to its high density and high speed. However, o move it into space application, it is quite complicated to handle it because of the following reasons: - Complex Behavior under radiation – No Rad Hard device available - Volatile – Data loss risk if any functional issue - Difficult to handle Micro-BGA for Space applications - Short life cycle – new device every 6 months That is the motivation to develop a RIMC IP core provided a full protection against the DDR2 radiation soft effects such as SEFI and SEU. From user point of view, all radiation protections are transparent, and the RIMC provides a standard AMBA/DFI compatible interface to targeted most space FPGAs. Figure1 shows the solution’s architecture overview. Figure 1: Overview ![RIMC2][1] II. RIMC ARCHITECTURE The RIMC is defined by 2 interfaces (see Figure 2): - The user interface, AMBA compliant. This interface contains at least one AHB bus, and may contain an optional APB bus for user dynamic configuration. These busses are compatible to AMBA 2.0 - The DDR PHY interface, compliant to DFI 2.1 (depends on different FPGAs) This interface is used to send commands and data to the DDR components through the DDR PHY. The RIMC controller can be configured by the core logic using 2 different AMBA interfaces: - Slave AHB interface with specific address mapping (1 area dedicated to DDR memory array and 1 area dedicated to internal registers) - Slave APB interface dedicated to internal registers Figure 2: RIMC Interface ![RIMC3][2] The RIMC is highly configurable to be compatible with most of user designs: - User data width (from x8 to x128) - Hamming or Reed-Solomon(RS) ECC selectable - Configurable up to 8 AHB slave interfaces - Configurable DDR2 ranks to increase memory capacity - Clock&ODT setting compatible with 3D PLUS modules - Capability to manage memory redundancy design The RIMC first version is to address FPGA development, and it is commercially available. III. MEMORY RADIATION ERRORS & IP CORE PROTECTIONS The DRAM radiation errors can be simply classified as below in 2 categories: Hard Errors and Soft Errors. The Hard Errors create irreversible errors when the threshold or limit have been passed. 3D PLUS propose a radiation tolerant DDR2 memory die with the guarantee of TID>100Krad(Si) and SEL>60Mev.cm²/mg. This paper will not present detail results on TID & SEL guarantee of the memory die. On the other hand, as semiconductor feature size scaling down, the soft errors (SEU and SEFI in case of DDR2) easily can be dominated events, especially SEFI, to DDR2 memories under radiation environment. However, each semiconductor, even each DDR2 Part Number from same semiconductor, will bring totally different SEU & SEFI results. To reach a real Rad-Hard DDR system, a well-evaluated specific DDR2 memory and its tailored controller, for example: identify memory different types of SEFI and select the correspondent mitigation strategies to guarantee no data loss, are mandatory. A. IP Core SEU Mitigation The RIMC can be configured at different types of ECC based on error rate tolerance, and here is an example of Reed-Solomon code as in figure 3 for 32b data and 50% overhead [RS(12;8), m=4, Global Bus = 48bits]. Figure 3: Example of data path with RS code, component Data Bus = 8 and DDR Data Bus = 32 ![RIMC4][3] As this RS ECC structure, The RIMC IP core(3D PLUS P/N: 3DIPMC700) can correct up to 8 bits error (row error) in one die per 48b, and 2 SEUs in the same address of different die per 48b. In case of scrubbing applied, the worst case (one particle create 2 upsets in 2 dice) in correctable error rate will be 3.8E-9 upset/day/module. Please note that 3DIPMC700 provides several different types of ECCs, and here is the error rate with Figure 3 data structure. The other ECCs (ex: Hamming) or other structures will bring other results. B. IP Core SEFI Protection Single Event Functional Interruption (SEFI) - a condition which causes a temporary non-functionality or interruption of normal operation induced by an energetic particle in the affected device, are very critical to space design. Mentioned at the beginning of this chapter, as feature size scaling down, the modern DRAM components have lower SEFI threshold and bigger cross section, which makes the SEFI easily becoming the dominated event. Moreover, unlike the SEU correctable by ECC, SEFI can easily bring system interruption or data loss and damage the whole sub-systems. Traditionally, SEFI mitigation is to power cycle or reset the component after SEFI happened, which means to restore or recover the component from a SEFI; However, power cycling will lead data loss, and in most case power lines are merged together, so not only the SEFI die data lost, but also all the dice managed by same power lines will have data loss. To avoid all these negative impacts from SEFI, a patent-pending SEFI protect technique has been designed and embedded in RIMC IP Core to prevent SEFI to replace traditional “after SEFI happened and recover” strategy. This SEFI protection is transparent to user and integrated in the RIMC IP core. Verification test had been performed at Radiation Effects Facility, University of Jyväskylä, Finland (RADEF) to confirm the protection, here below is the result: Table 1: 3D PLUS DDR2 Memory module SEFI results under RIMC Protection ![RIMC5][4] Ion LET[MeV/mg/cm2] Rang[microns] Fluence[p/cm²] Sample/Runs SEFI 20Ne+6‡ 3.63 146 >1E6 1 No 40Ar+12‡ 10.2 118 >1E6 5 No 56Fe+15 18.5 97 >1E6 5 No 82Kr+22 32.2 94 >1E6 >10 No 131Xe+35 60.0 89 >1E6 6 No No SEFI observed till LET>60Mev-cm2/mg. As a general use purpose controller IP core, RIMC is designed for any JEDEC standard DDR2 SDRAM. But please note that this patent-pending SEFI protection technique is not a universal solution, and only can be used to the die embedded in 3D PLUS DDR2 modules. On the other words, RIMC IP core can be used with any other DDR2 die, and the SEFI protection should be deactivated. IV. CONCLUSION A RIMC IP core has been proposed to reach a radiation hardened DDR2 solution. The solution includes the radiation tolerant DDR2 module with SEL immune and TID guarantee and RIMC IP core to specifically manage the SEU and SEFI of the DDR2 module to reach: TID>100Krad(Si) SEL immune > 80Mev.cm2/mg SEU immune by design (3.8E-9 upset/day/module) SEFI immune by design (LET>60Mev-cm2/mg) [1]: http://gdriv.es/rimc/rimc2.jpg [2]: http://gdriv.es/rimc/rimc3.jpg [3]: http://gdriv.es/rimc/rimc4.jpg [4]: http://gdriv.es/rimc/rimc5.jpg
        Speakers: Mr Charles Sellier (3D PLUS) , Mr Pierre-Xiao WANG (3D PLUS)
    • 08:30 09:00
      Registration 30m

      Open from 8:30 to 12:00

    • 09:00 09:05
      ESA DSP Day - Day 2 Introduction
      Convener: Dr Roland Trautner (ESA/ESTEC)
      • 09:00
        ESA DSP Day 2016 - Day 2 Introduction 5m
        Speaker: Dr Roland Trautner (ESA/ESTEC)
        Slides
    • 09:05 11:05
      Session 5: DSP Software and Applications
      Convener: Mr Olivier NOTEBAERT (Airbus Defence and Space)
      • 09:05
        DSP Benchmark Results of the GR740 Rad-Hard Quad-Core LEON4FT 30m
        ***ABSTRACT*** The GR740 microprocessor device is a SPARC V8(E) based multi-core architecture that provides a significant performance increase compared to earlier generations of European space processors. The device is the result the European Space Agency's initiative to develop a European Next Generation Microprocessor (NGMP). Engineering models have been manufactured in 2015 and tested during the first quarter of 2016. Space qualification of flight models is planned to start in the second half of 2016. GR740 is the highest performing European space-grade general purpose microprocessor and, due to the presence of four powerful floating-point units, it is suitable for executing DSP applications. This abstract provides an overview of the GR740 and a subset of the benchmarks used within the ESA activity's functional validation effort. A more in-depth description of the architecture and results of DSP benchmarks will be added to the final paper and presentation. ***BACKGROUND*** The LEON project was started by the European Space Agency in late 1997 to study and develop a high-performance processor to be used in European space projects. Following the development of the TSC695 (ERC32) and AT697 processor components in 0.5 and 0.18 μm technology respectively, ESA initiated the Next Generation Microprocessor (NGMP) activity targeting a European Deep Sub-Micron (DSM) technology in order to meet increasing requirements on performance and to ensure the supply of European space processors. Cobham Gaisler was selected to develop the NGMP system that is centred around the new LEON4FT processor. Throughout 2014 and 2015, the architecture was designed and manufactured in the C65SPACE platform from STMicroelectronics. ***ARCHITECTURAL OVERVIEW*** The figure below shows an overview of the GR740 architecture. The four LEON4FT processors are connected to a shared bus which connects to a 2 MiB EDAC protected Level-2 cache before reaching external EDAC protected SDRAM. Each LEON4FT processor has a dedicated pipelined IEEE-754 floating-point unit. The design makes use of extensive clock gating and the processors can be put in a power-down mode to conserve power when some or all processor cores are unused. While the GR740 implementation of LEON4FT lacks support for dedicated multiply-and-accumulate instructions this is mitigated by the presence of the large number of processor registers, L1 cache memory and high operating frequency. ![enter image description here][1] The main communication interfaces of the device include eight external SpaceWire ports connected to an on-chip SpaceWire router, two 10/100/1000 Mbit Ethernet ports, MIL-STD-1553B and 32-bit PCI. The four parallel CPU / FPU cores, each running on dedicated separate instruction and data L1 caches (Harvard architecture), at 250 MHz clock frequency, can theoretically provide up to 1 Gflop/s in single or double precision. Together with the multiple Spacewire and Ethernet interfaces, this makes the GR740 suitable for DSP applications, provided that the application implementation succeeds in making an efficient parallelisation and streaming of data across the shared on-chip buses. This shall be demonstrated with the implementation of dedicated DSP benchmarks, as for example those suggested in [1]. The NGMP architecture has already been evaluated in an effort where the GAIA VPU application was adapted to take advantage of a multi-core system. The conclusion from this effort was that the GR740 is fast enough to run the GAIA VPU application [2]. ***FUNCTIONAL VALIDATION AND DSP BENCHMARKS*** The functional validation of the GR740 device builds on existing tests used in the frame of the NGMP activities. The tests include both functional and performance benchmarks. Benchmarks that may be of particular interest to a DSP audience include: - Run of the SPEC CPU2000 benchmarks - Run of PARSEC 2.1 benchmarks - Benchmarks developed by Barcelona Supercomputing Center in the frame of the ESA contract Multicore OS Benchmark will be employed to analyse the capabilities of the GR740 to execute parallel workloads. - EEMBC benchmarks: CoreMark, CoreMark Pro, Autobench, FPMark and Multibench. The results of the functional validation effort will be summarised in a public technical note. The note will contain benchmark results and will also compare the GR740 results with other existing space-grade microprocessors. The presentation will describe the results from the functional validation. In addition to this, the functional validation will be extended with DSP benchmarks targeted at the audience at the ESA DSP Day. ***CONCLUSION*** The GR740 is a SPARC V8(E) based multi-core ar­chitecture that provides a significant performance in­crease compared to earlier generations of European space processors, with high-speed interfaces such as SpaceWire and Gigabit Ethernet on-chip. The platform has im­proved support for profiling and debugging, and software tools have been upgraded to this new architecture. Moreover, a rich set of software is immedi­ately avail­able due to back­ward compatibility with ex­isting SPARC V8 software and LEON3 board support pack­ages. The GR740 constitutes the engineering model of the ESA NGMP, which is part of the ESA roadmap for standard mi­croprocessor components. It is developed under ESA contract, and it will be commercialised under fair and equal conditions to all users in the ESA member states. The GR740 is also fully developed with manpower loc­ated in Europe, and it only relies on European IP sources. It will therefore not be affected by US export regulations. The functional validation effort aims to validate functionality of the device and of the development board that will be made available to the space industry. The GR740 is the highest performing European space-grade processor to date and results of DSP benchmarks will be presented to allow industry to assess the GR740's suitability for DSP applications. News about the GR740 device can be found at the following link: http://www.gaisler.com/gr740 ***REFERENCES*** [1] Next Generation Space Digital Signal Processor Software Benchmark , Issue 1.0, TEC-EDP/2008.18/RT, 01 December, 2008 [2] RTEMS SMP Executive Summary, Issue 1, Revision 2, RTEMSSMP-ES-001, March 2015, http://microelectronics.esa.int/ngmp/RTEMS-SMP-ExecSummary-CGAislerASD-OAR.pdf [1]: http://gaisler.com/tmp/index.png
        Speaker: Dr Javier Jalle (Cobham Gaisler)
        Paper
        Slides
        summary
      • 09:35
        A Lightweight Operating System for the SSDP 30m
        A common problem of space missions is the limited processing power of available space-qualified hardware. In recent years, ESA has been pursuing the development of an ITAR-free next generation payload processor. One of the outputs of this effort is a prototype SoC called the MPPB (Massively Parallel Processor Breadboard) developed by Recore System and built around the Very Long Instruction Word Xentium DSP architecture designed by the same company. In this platform, a LEON processor is acting as a supervisor, controlling a Network-on-Chip (NoC) with multiple DSPs, memory and I/O devices attached to it. In the course of the NGAPP (Next Generation Astronomy Processing Platform) activities, an evaluation of the MPPB was performed in a joint effort of RUAG Space Austria and the Department of Astrophysics at the University of Vienna. It was found that, given the highly innovative nature of this new processing platform, a novel approach was needed regarding the management of system resources, DMA mechanics and DSP program design for best efficiency and turnover rates. Consequently, the University of Vienna developed an experimental operating system to stably drive the DSP cores and the MPPB close to its performance limit. This is achieved by splitting processing tasks into a pipeline of small units (kernels) that are dynamically scheduled to run on the Xentium DSPs as required by the amount of data in the pipeline stages, thereby overcoming bottlenecks resulting from memory transfer overheads and cache sizes that would inevitably emerge when using large, monolithic programs with the particular characteristics of the MPPB. At present, activities are carried out by Thales Alenia Space España and Recore Systems in an effort to create the Scalable Sensor Data Processor (SSDP), where an ASIC with adapted specifications is being developed from the MPPB. In order to support this new hardware, a more refined version of the experimental operating system is under development at the University of Vienna that aims to become fully space-qualifiable, supporting applicable documentation and S/W standards. The software will be tailored to the NoC concept present in the SSDP and is to be optimised for best performance in key areas of system and resource management. These include fast and efficient interrupt handling to ensure fast response times and high memory throughput for DMA transfers that service the Xentium data caches and fast I/O interfaces like SpaceWire or ADC/DAC. Supporting functionality, for example device drivers, threads and schedulers, timing and a system configuration/information interface will be provided. Effort will be made to keep CPU and memory footprints at a minimum, so the LEON processor is available for duties other than DSP and data processing control, such as handling of telecommands or instrument related control tasks. A major aim is to make the operating system as easy to use as possible by providing appropriate, well designed interfaces in order to keep the need for configuration and extra programming effort at a minimum. To encourage use, modification and redistribution of the operating system, it will be made available under an open-source license, including all drivers, modules and available DSP kernels.
        Speaker: Mr Armin Luntzer (University of Vienna)
        Paper
        Slides
        summary
      • 10:05
        High-performance DSP for onboard image processing 30m
        ABSTRACT The evolution of the Earth Observation mission is driven by the development of new processing paradigms to facilitate data downlink, handling and storage. Next generation planetary observation satellites will generate a great amount of data at a very high data rate, for both radar based and optical core applications. Real-time onboard processing can be the solution to reduce data downlink and management on ground. Not only commonly used image compression techniques (like e.g. JPEG2000) and signal processing can be performed directly on board, but also compression techniques based on more detailed analysis of image data (like e.g. frequency/spectral analysis). The MacSpace RC64 is a prototype DSP/ASIC for novel onboard image processing, which is being designed, developed and benchmarked in the framework of an EU FP7 project and targets these new demands for making a significant step towards exceeding current roadmaps of leading space agencies for future payload processors. The DSP featuring the CEVA X-1643 DSP IP core will deliver performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. INTRODUCTION Nowadays, leading space agencies plan for high resolution and wide swath radar imaging systems aboard satellites such as the one to be employed in future Sentinel-1 (HRWS) or potential Venus orbiter missions. Part of the processing could be shifted from the ground station to the satellite itself, requiring powerful real-time on-board processing [1]. Typical applications include, SAR imaging and data compression. A large set of these applications comprise of computationally intensive kernels. These ambitions – far beyond well-known benchmarks, comprising of mostly basic signal processing algorithms like Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filtering – depend on the availability of flexible and scalable hardware and software solutions, since applications most likely will change and develop over time and therefore space systems will need to adapt within limited time frames. Unlike currently employed applications such as e.g. FFT processing and BAQ compression on SAR satellites that usually do not change during the life-time of a satellite and therefore are mostly realized in hardware (e.g. FPGA accelerators). More modern applications - due to longer development time and relatively high development costs - can’t be implemented on special purpose hardware accelerators economically. We have detected the need for a platform that allows enough flexibility for space application developers and mission planners in order to determine feasibility of new ground breaking missions and to determine their parameters. The aim of the MacSpace project is to drive on-board processing of complex applications such as SAR imaging forward, eliminating the need for continuous transfer of huge data streams to ground stations, saving significant energy, time and bandwidth that are required for data transfers and especially for planetary observation. Besides enabling latency critical workloads, energy for data transmission can be saved and spent instead for onboard high-performance computing. One key challenge of MacSpace therefore is matching potential application requirements. SAR IMAGE PROCESSING Modern Synthetic Aperture Radar (SAR) systems are continuously developing into the direction of higher spatial resolution and new modes of operation. This requires the use of high bandwidths, combined with wide azimuthal integration intervals. For focusing such data, a high quality SAR processing method is necessary, which is able to deal with more general sensor parameters. Wavenumber domain (Omega-K) processing is commonly accepted to be an ideal solution of the SAR focusing problem. It is mostly applicable on spaceborne SAR data where a straight sensor trajectory is given. Therefore, within the MacSpace project the TU Braunschweig in close connection with the DLR is conducting experimental benchmarks on a representative SAR application excluding preprocessing steps. The application consists of: i) Range FFT ii) Range compression iii) Modified Stolt Mapping iv) Range IFFT v) Azimuth FFT vi) Azimuth Compression vii) Azimuth IFFT Computation-wise one single RC64 chip could be capable of processing data of 8192x8192 complex values (single precision floating point, i.e. in total 512MB) in under 2 seconds @ 300MHz and 100% compute utilization (based on a computation count: 60G Floating Point Operations @ 38 GFLOPS). Since the onboard data bandwidth (per core: L1 data - peak 128bit read/write per cycle per core from/to registers, L1 from/to shared memory ('L2') 128bit @~50% utilization read and 32bit write) potentially can sustain the demand by computations, reaching the best-case performance will be a matter of latency hiding. In the worst-case scenario, we still expect the application to finish processing the above described data in under 1 minute. MACSPACE DEMONSTRATOR The development of a MacSpace demonstrator is part of the project to validate the usability and functionality of the system. The processor architecture is implemented in a high-performance FPGA (Xilinx Virtex 7) representing the MacSpace RC64 prototype, which executes the image processing. A personal computer performs the management and the payload data handling. The GSEOS V software package is used to send preprocessed radar data, control and monitor the prototype as well as to analyse the results and qualify the performance. Its high computing performance of 150 GOPS and 38 GFlops per RC64 chip, which could scale to an interconnected system that meets any defined performance level, can maintain high processing resources utilization using innovative parallel programming technics. The main approach is to parallelize compute kernels on a base of sufficiently small-split independent tasks that each work on local data, while using shared memory. A hardware (task) scheduler dynamically allocates, schedules, and synchronizes tasks among the parallel processing cores according to the program flow. Hence, it reduces the need for an operating system (OS) and eliminates large software management/execution overhead. No OS is deployed to the cores. RELATED WORK AND COMPARISON Most existing processors for space applications, such as Atmel AT697 [5], Aeroflex UT699 [6], Aeroflex Gaisler GR712RC [7] and BAE Systems RAD750 [8], provide performance levels below 1,000 MIPS, and are thus unsuitable for executing high-performance “next generation digital signal processing” (NGDSP) tasks in space missions [1]. While NGDSP requirements are listed at 1,000 MIPS/MFLOPS, a more practical goal is 10,000 MIPS. Even the fastest, currently available space processor, SpaceMicro Proton200K [9], achieves only about 4,000 MIPS/900MFLOPS. Performance of some space processors versus year of introduction is plotted in figure 2. ![enter image description here][1] Figure 2: Performance Comparison of the RC64 based on MacSpace RC64 Prototype with other space processors Recently, the US government has adopted Tilera’s Tile processor for use in space, in the framework of the OPERA program and the Maestro ASIC [10]. Integrating 49 triple issue cores operating at 310 MHz, it is expected to deliver peak performance of 45,000 MIPS. Software development experience for the Maestro chip has encountered difficulties in parallelizing applications to the mere 49 cores of the Maestro. Some of the developments have underestimated the inter-core communication latencies involved in the tiled architecture of Maestro. Due to such difficulties, programmers are forced to cram multiple different applications into the many-core, resulting in additional difficulties regarding protection of each application from the other ones. REFERENCES [1] ESA, Next Generation Space Digital Signal Processor (NGDSP), http://www.esa.int/TEC/OBDP/SEMR88NO7EG_0.html, July 2012 [2] Ginosar, Aviely et al., RC64: A Many-Core High-Performance Digital Signal Processor for Space Applications, DASIA 2012 [3] Gao, B.-C., A. F. H. Goetz and W. J. Wiscombe, Cirrus Cloud detection from airborne imaging spectrometer data using the 1.38 μm water vapor band, GRL,20,301-304, 1993 [4] Hyperspectral Image Processing for Automatic Target Detection Applications Dimitris Manolakis, David Marden, and Gary A. Shaw, VOLUME 14, NUMBER 1, LINCOLN LABORATORY JOURNAL, 2003 [5] Atmel Corp., Rad-Hard 32 bit SPARC V8 Processor AT697E (datasheet), http://www.atmel.com/Images/doc4226.pdf [6] Aeroflex Gaisler, UT699 32-bit Fault-Tolerant LEON3FT SPARC V8 Processor, http://www.gaisler.com/index.php/products/components/ut699 [7] Aeroflex Gaisler, GR712RC Dual-Core LEON3FT SPARC V8 Processor, http://www.gaisler.com/index.php/products/components/gr712r c [8] BAE Systems, RAD750®radiation-hardened PowerPC microprocessor (datasheet), http://www.baesystems.com/download/BAES_052281/Space- Products--RAD750-component [9] Space Micro, Proton200k DSR-based SBC, http://www.spacemicro.com/assets/proton-200k-dspv22.pdf [10] M. Malone, OPERA RHBD Multi-Core, MAPLD, 2009 [1]: http://amicsa.esa.int//2016/images/contrib/Macspace_RC64.png
        Speaker: Mr Jamin Naghmouchi (TU Braunschweig)
        Paper
        Slides
        summary
      • 10:35
        Space Debris Detection on the HPDP, a Coarse-Grained Reconfigurable Array Architecture for Space 30m
        ## Introduction## Stream processing, widely used in communications and digital signal processing applications, requires high-throughput capabilities that is achieved in most cases using ASIC designs. But, lack of programmability is an issue especially in space applications, which use on-board components with long life-cycles requiring applications updates. On the other hand, FPGA allows reconfigurable hardware design at gate level, offering more flexibility than an ASIC at expenses of higher power consumption, more silicon and at a relatively reduced maximum clock frequency [2]. However, fine granularity reduces performance in FPGA because of the complexity of the programmable connections used to build logic blocks [3]. As a result, architectures are evolving towards hardware with reconfigurable capabilities that integrate modules to efficiently perform frequently used operations. The eXtreme Processing Platform (XPP) is the core of the High Performance Data Processors (HPDP) architecture [4]. The XPP allows runtime reconfiguration of a network of coarse-grained computation and storage elements. The algorithm's data-flow graph is implemented in configurations, in which each node is mapped to fundamental machine operations executed by a configurable ALU [5] The present work aims to determine the effectiveness, portability and performance of an image processing algorithm in the HPDP architecture. Space debris is a major issue for operational satellites and spacecraft. A Space Based Space Surveillance (SBSS) mission using an optical telescope has been proposed [1] in order to detect and track such debris. The required frame rate for the instrument calls for an efficient on-board image processing implementation. Such on-board data reduction can be implemented by detecting features of interest (debris, stars) while omitting the remaining image content (noise, space background). ## THE XPP AS THE CORE OF THE HPDP## The XPP Core consists of three types of Processing Array Elements (PAE): arithmetic logic unit PAE (ALU-PAE), random access memory with I/O PAE (RAM-PAE) and the Function PAE (FNC-PAE). ALU-PAE and RAM-PAE objects are arranged in a rectangular array, called the XPP Data-flow Array [6]. For the implementation of the feature detection algorithm the XPP-III 40.16.2 core is used, consisting of 40 ALU-PAE objects arranged in a 5x8 array, 16 RAM-PAE and two FNC-PAE. For the HPDP project the XPP core has been selected by Airbus DS due to the availability as HDL source code among others. This enables the implementation on the STM65nm semiconductor technology, using a radiation hardened library. This makes the resulting HPDP chip suitable to operate in all earth orbits and beyond. The development of this chip is currently on-going, first prototypes are expected in the first half 2016. ## MAPPING THE SPACE DEBRIS DETECTION DATA-FLOW GRAPH## The boundary tensor has been chosen as the feature detection algorithm and is constructed combining the results of applying a set of polar separable filters to the input image [7]. The convolution process accounts for 80\% of the required data processing. The proposed implementation takes advantage of properties of the filter kernels and performs simplifications in the data representation with the objective of reducing operations, XPP array resources use and cycle-count for data transactions with the system's main memory: - The reference design [8] requires floating-point arithmetic. However, convolution is implemented using fix-point arithmetic in this work in order to reduce hardware resources use and guarantee a predictable execution time of operations, which is critical for real-time applications. - A trade-off between accuracy and performance is possible: the least significant bit (LSB) of the input pixels is truncated, then all computations fit into 16 bits, and the implementation requires the transfer of half the data volume, at expenses of inducing an error in the detection result. - Symmetry in a kernel is advantageous for the implementation, because it reduces by as much as half the number of necessary multiplications between kernel elements and pixels. - Used kernels are derived from normalised Gaussian functions, then it is possible to demonstrate that no overflow in convolution operations occurs. Finally, boundary tensor calculation is performed only once at the end of the algorithm and its complete implementation fits in a single XPP array configuration. For this reason, there are no intermediate values that must be temporarily stored in the system memory to be streamed-back to the XPP array for further processing, therefore calculations are carried out using the full bit-width. ## RESULTS ## The runtime estimates are derived from a cycle-accurate simulation of the XPP array. The maximum average resultant throughput is 3.98 Bytes/cycle, which is achieved by the configurations computing convolution with odd symmetry kernels. The expected HPDP hardware specification integrates, among other elements, a single-port SRAM achieving 800 MBytes/s, and an XPP array working at 200 MHz clock. As a result, the minimum bandwidth to provide and store-back a continuous data stream to the XPP array is 1592 MBytes/s. Therefore, the performance of the algorithm's execution on the specified HPDP hardware is determined by the memory speed. Based on the number of write and read operations needed for the complete algorithm using sub-image processing, the estimated algorithm's execution time for the expected HPDP hardware is 734 ms for a 16 bits 2048x2048 pixels input image. In terms of effectiveness, for each detected streak obtained from the HPDP simulation, there are approximately 10% less detected pixels compared with the reference implementation, as shown in the following image for an input containing a streak with an SNR of 7.19 dB. The error is negligible since the detection information per object can then be used to store full streak pixel values in order to not lose accuracy with respect to the position and brightness in a further processing step on-ground. ![Comparison between reference and HPDP implementation.][1] ## CONCLUSIONS ## It has been shown that the boundary tensor algorithm can be mapped to a data-flow graph and a simple control-flow is only required for filter kernel update, border replication and pipeline cleaning tasks. Thus, the XPP array is appropriate for its implementation, because makes possible to exploit pipeline parallelism in convolution's multiplication and addition operations, and task parallelism, since four consecutive streams are used to compute the convolution of four pixels simultaneously, without data dependencies, reaching in average 4.7 GOp/s, for 16-bit fixed-point operations. The utilisation of 99% of XPP array computation elements (e.g. ALU-PAE), and the use of the maximum transfer mode of the 4D-DMA, shows that this implementation is taking advantage of all the capabilities of the architecture. Finally, it is demonstrated that the LSB truncation is an effective alternative to meet the real-time requirement because the gain in performance is greater (twice as fast) than the error caused in the detection, evidenced by a loss of only 10% of high-detection pixels. ## REFERENCES## [1] Utzmann, J., Wagner, A., Silha, J., Schildknecht, T., Willemsen, P., Teston, F., Flohrer, T., Space-Based Space Surveillance and Tracking Demonstrator: Mission and System Design. 65th International Astronautical Congress, Toronto, Canada (2014). [2] Bailey, D.: Design for Embedded Image Processing on FPGAs John Wiley & Sons (2011). [3] Bobda, C., Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications. Springer Netherlands (2007). [4] Syed, M., Acher, G., Helfers, T., A High Performance Reliable Dataflow Based Processor for Space Applications. In: Proceedings of the ACM International Conference on Computing Frontiers, 1-4, ACM, New York, USA (2013). [5] Sch¨uler, E., Weinhardt, M., XPP-III: Reconfigurable Processor Core. In: Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach, Chap. 6, Springer Netherlands (2009). [6] PACT XPP Technologies AG, XPP-III Processor Overview White Paper. Germany (2006). [7] K¨othe, U., Integrated edge and junction detection with the boundary tensor. In: Computer Vision, 2003. Proceedings. Ninth IEEE International Conference on, 424-431 (2003). [8] VIGRA Homepage, Heidelberg Collaboratory for Image Processing. http://ukoethe.github.io/vigra/ [1]: http://s15.postimg.org/43vmmj1cb/Results.png
        Speaker: Mr Diego Suarez (Technische Universität München)
        Paper
        Slides
        summary
    • 11:05 11:30
      Coffee break
    • 11:30 12:30
      Session 6: IP Cores, FPGAs, and their Synergies with DSPs
      Convener: Mr Jan Andersson (Aeroflex Gaisler)
      • 11:30
        Multi-core DSP sub-system IP 30m
        **Architecture** The multi-core DSP sub-system comprises the following key building blocks: • The Xentium® is a programmable high-performance DSP processor core that is efficient and offers high-precision; • Network-on-Chip (NoC) technology provides sufficient bandwidth, flexibility and predictability which are required for interconnecting DSP cores and I/O interfaces in streaming DSP applications. The presented multi-core DSP sub-system consists of programmable fixed-point (and floating-point in the future) DSP cores that are connected by a NoC. After initialization by the host processor, the multi-core DSP sub-system will autonomously run compute-intensive DSP functions. **Network-on-Chip** The NoC provides the bandwidth and flexibility that is required for streaming DSP applications. The communication bandwidth in a NoC scales with the number of cores. In conventional bus architectures, additional processors share the original bandwidth and will eventually create a bottleneck. A NoC ensures predictable performance due to its point-to-point connections, in contrast to the unpredictability of a shared bus. Moreover, NoCs allow disabling inactive parts of the network, which is essential for energy-efficiency and dependability. Using transparent I/O interfaces it is possible to extend the NoC across the chip boundaries. Several I/O interfaces are available on the multi-core DSP architecture, such as SpaceWire bridge interfaces, bridges to external Analog-to-Digital Convertor (ADC) and Digital-to-Analog Convertor (DAC) devices. All NoC interfaces employ memory-mapped communication. **Xentium DSP** The Xentium is a programmable high-performance 32/40-bit fixed-point DSP core for inclusion in multi-core systems-on-chip. High-performance is achieved by exploiting instruction level parallelism using parallel execution slots. The Very Long Instruction Word (VLIW) architecture of the Xentium features 10 parallel execution slots and includes support for Single Instruction Multiple Data (SIMD) and zero-overhead loops. The Xentium is designed to meet the following objectives: high-performance, optimized energy profile, easily programmable and memory mapped I/O. **Xentium DSP – Datapath** The Xentium datapath contains parallel execution units and register files. The different execution units can all perform 32-bit scalar and vector operations. For vector operations the operands are interpreted as 2-element vectors. The elements of these vectors are the low and high half-word (16-bit) parts of a 32-bit word. In addition several units can perform 40-bit scalar operations for improved accuracy. All operations can be executed conditionally. The Xentium datapath provides powerful processing performance: 4 16-bit MACs per processor clock cycle or 2 32-bit MACs per cycle or 2 16-bit complex MACs per cycle. Currently, the fixed-point Xentium datapath is being upgraded to support floating-point operations as well. **Xentium DSP – Tightly-coupled Data Memory** Private local memories are available y is available at the Xentium DSP. The tightly-coupled data memory is organized in parallel memory banks to allow simultaneous access by different resources. The data memory can be simultaneously accessed by the Xentium core as well as other cores connected through the NoC. By default the data memory in the Xentium tile is organized in 4 banks of 4 kBytes each, implemented using SRAM cells. The size of the memory banks is parametrizable at design-time. **Software Development and Debugging** The software development for the Xentium is supported by a C compiler, an assembler, a linker, a simulator, a debugger, and a number of utilities. The compiler translates C source code into Xentium assembly language source code. In order to ease the software development on the multi-core DSP architecture, the architecture has been equipped with multi-core DSP debug infrastructure. The Xentium DSP cores have integrated hardware debug support to intrusively debug all registers in the Xentium datapath. Also, a cross-trigger unit allows the debugging of multiple Xentium cores in parallel. The debug infrastructure interfaces with standard GDB debug tools.
        Speaker: Dr Gerard Rauwerda (Recore Systems)
        Paper
        Slides
        summary
      • 12:00
        DSP and FPGA: Competition, Synergy, and Future Integration in Space ASICs 30m
        Digital Signal Processors (DSPs) have been popular devices for computation-intensive data processing for many decades. In comparison to General Purpose Processors (GPPs), their specific architectural designs support efficient processing of digital data via separate data and instruction memories, combined operations such as multiply-accumulate (MAC), hardware support for efficient loop execution, execution of multiple parallel operations (SIMD / VLIW), Direct Memory Access (DMA) mechanisms and other specific features. Ever increasing clock speeds and, more recently, many-core designs have led to significant performance increases, a trend that is still continuing. In parallel, programmable logic devices (PLDs) have seen a dramatic evolution in terms of performances, popularity and capabilities of programming tools. Originally starting from relatively modest complexity level that allowed the implementation of glue logic and other specific circuitry, the recent generation of programmable devices, in the form of memory based Field Programmable Gate Arrays (FPGAs), allows not only to complement dedicated Application Specific Integrated Circuits (ASICs) including GPPs and DSPs, but can replace them entirely in many application cases. The application spectrum for programmable devices with respect to GPPs and DSPs has therefore evolved from a complementary, supportive role to a more competitive/ synergetic one. In the commercial world, a next step – the integration of FPGA and GPP / DSP – is already taking place [1, 2, 3]. After the integration of hard macro processors in available commercial FPGAs, large processor manufacturers are integrating FPGA dies or -fabric in their high performance processors for purposes such as programmable functionality extensions like application specific co-processor implementations [4] . It is common knowledge that commercial processor technology trends are arriving in the space processor technology area with a typical delay of 10-15 years. Therefore it is reasonable to assume that the integration of processors / DSPs and FPGAs on the same chip is about to arrive in qualified space ASICs around 2020, probably first in the form of Multi-Chip Modules (MCMs) or in FPGAs with integrated processor macros, and – possibly some years later - followed by DSPs and processors with integrated FPGA fabric. This paper will focus on the integration of FPGA fabric in future DSP Systems on Chip (SoCs). Already today, the advantages of integrated FPGA fabric on space qualified DSP chips are obvious. Many application cases require the combination of processor chips with separate ADC, DAC, analogue frontend chips, specific interface chips, and specific co-processors. The necessary glue logic is typically provided via a separate, suitably sized FPGA. Integration of glue logic in FPGA on the processor chip allows to reduce the component count and cost, saves printed circuit board area and mass, increases reliability, lowers power consumption, and ensures the same level of radiation hardness for processor and logic. Additional use cases of similar complexity could be the on-chip FPGA implementation of specific interface types, related protocols, and similar functionality. Another application area, requiring more capable FPGA fabric, is the on-chip implementation of co-processor or pre-processor functions. This might range from simple functions like specific data operations or an FIR / FFT accelerator to FPGA based data compression algorithms or even the integration of full-fledged software programmable VLIW DSP IP cores, in all cases possibly combined with additional logic and interlinks as required by the specific application case. Finally, the integration of FPGA fabric in the heart of a processor core can allow the implementation of specific instructions that may speed up particular type of processor operations significantly. For the integration of FPGA fabric on digital processors, specifically future many-core space DSPs, there are multiple options. An FPGA can be integrated as a separate die in a MCM, or with the processor cores on the same die. For MCM designs, dies exist from several companies. For on-die integration, both fully synthesizable e-FPGA designs as well as full-custom high density FPGA IP are available from European and other sources. A large trade space exists for the number, size, type and complexity of FPGA tiles on a digital chip. Both SRAM based and Flash memory based designs are available, with some specific restrictions to ASIC processes. The integration of analogue / mixed signal design elements on the same chip represents an additional dimension in the design space; also here, restrictions to ASIC processes and available IP apply.
        Speaker: Dr Roland Trautner (ESA/ESTEC)
        Paper
        Slides
        summary
    • 12:30 12:55
      Round Table Discussion - DSP and FPGA

      (description)

      Convener: Dr Roland Trautner (ESA/ESTEC)
      • 12:30
        Open discussion on synergies of DSP and FPGA IP, related user requirements, and industrial views 25m
        Speaker: Dr Roland Trautner (ESA/ESTEC)
    • 12:55 13:00
      ESA DSP Day 2016 - Wrap-up and Conclusions
      Convener: Dr Roland Trautner (ESA/ESTEC)
    • 13:00 14:00
      Lunch 1h