# AMICSA & DSP 2016

Europe/Amsterdam
Gothenburg, Sweden

, ,
Description

# ESA's AMICSA

## 6th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications 12th - 15th June 2016

Organized in collaboration with ESA, Cobham Gaisler and our Sponsors, provides an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

• Radiation Effects on analogue and mixed-signal ICs
• Methodologies for Radiation Hardening on analogue circuits at cell-, circuit-, and system design level
• Radiation-hardened technologies for analogue ICs
• Radiation tests of analogue and mixed-signal ICs
• Qualifying and quantifying radiation-hardness of analogue circuits
• Space Applications for analogue and mixed-Signal ICs
• Analogue intellectual property and re-usability of analogue circuits in space
• Needs and Requirements for analogue and mixed-signal ICs in future space missions
• In-orbit Experiences and flight heritage of analogue and mixed-signal ICs

# ESA's DSP Day

## 3rd ESA workshop on Digital Signal Processing for Space Applications 15th - 16th June 2016

Organized this year in conjunction with AMICSA, provides an overview on relevant development roadmaps, updates on Digital Signal Processing technology for space applications, and the results of contractual activities for the development of DSP rad-hard components, related equipment, IP cores, and software.

• DSP IP cores and related IP for future SoC designs
• Space qualified DSP components
• COTS DSP components for space applications
• DSP boards, software development environments, libraries and related software
• Test, verification and qualification of DSP chips
• Status and results of DSP related ESA contracts
• DSP and FPGA: synergy, competition, and future integration
• Requirements and needs for future space DSPs
• Sunday, 12 June
• 17:00 19:00
Welcome Reception and Registration 2h
• Monday, 13 June
• 08:30 09:00
Registration 30m

Open from 8:30 to 17:00

• 09:00 09:40
AMICSA: Welcome and Introduction
Conveners: Mr Boris Glass (ESA) , Mr Sandi Habinc (Aeroflex Gaisler AB)
• 09:40 10:40
Space applications for analogue and mixed-signal ICs
Convener: Mr Angelo Consoli (Saphyrion)
• 09:40
Rad-Hard Microcontroller For Space Applications 20m
Speakers: Mr Fredrik Johansson (Cobham Gaisler) , Mr Jan Andersson (Aeroflex Gaisler)
• 10:00
Digital Programmable Controller (DPC) : from Concepts to Space Applications 20m
The presentation covers the key features of the Digital Programmable Controller ASIC (DPC) that have been validated during the development phase. It includes informations regarding radiations, explanations on the qualification process and associated TRLs, NEOSAT applications including analog IP and reuse of analog circuits in space, and other applications developed with partners
Speaker: Mr Marc Fossion (Thales Alenia Space Belgium)
• 10:20
MEMS Gyroscope Demonstration for Space Application, using a DPC 20m
This paper reports the prototyping and performance evaluation of a vibrating structure connected to the Digital Programmable Controller (DPC) developed by Thales-Belgium (TAS-B) in a gyroscope application. ONERA has been developping vibrating MEMS inertial sensors for various applications. The VIA cell (Vibrating Beam Accelerometer family) is already in use in the french civil and defence industry. The VIG cell (Coriolis Vibrating Gyroscope family) has been proposed for space applications, in the frame of low cost assistance gyroscope associated with star trackers on satellite platforms : detumbling, slowing down satellite rotation to allow star tracker acquisition or recovery. During previous activities several aspects of the VIG have been investigated, in the objective of a future qualification. The gyroscope quartz cells endured radiations successfully up to geostationary dose, and could also withstand launcher vibrations. Shocks were also acceptable with intercalated passive absorber. Concerning electronics, the design and realization of an ASIC was initiated, but prohibitive cost prevented from further development. Nevertheless it was assessed that the electronic architecture of the ONERA gyroscope was compatible with the DPC developed by TAS-B. Electronic architecture of the gyroscope has been mapped on the DPC cores and peripherals, and requirements set in terms of A/D D/A converters, voltages, CPU usage, and communication with host. Once the chip was released recently, the opportunity to build a demonstrator was found with the french space agency. A DPC Reference Kit (DRK) is used in this project. It consists in a true qualified DPC, mounted on an evaluation board with power supplies, I/O connectors and programmer access through JTAG. The DRK comes together with software tools (compiler, debugger, configuration manager), offering the developper a complete toochain from C source code to oscilloscope view of signals. In the present work, the core functions of the gyroscope application have been developed and characterized. First a Direct Digital Synthesizer (DDS) has been implemented with a particularly high resolution of 0.001 Hz, in order to accurately drive at resonance the high quality factor vibrating cell. A pair of ADC are operated synchronously with the synthesizer to acquire the amplitude and phase of Drive and Sense signals coming out of the vibrating cell. ADC are digitally demodulated in real time (~100 kHz) using the hardware Multiplier/Accumulator of the DPC, and deliver in-phase and quadrature components to the second DPC core. Further processing is performed, such as an embedded PLL for the resonator, and a decimation filter to scale down the raw data stream to the sampling rate configured by the user, which takes place in a standard desktop computer running the demonstration OBC software. The gyroscope data frames are composed and transmitted by the third core on a serial port. All these functions perfectly match the intentional asymmetric core design of the DPC, and all three cores are in use in the application. The program memory is tiny for each core (4K, 8K, 16K), but keeping an eye on assembler generated by the compiler allows the programmer to write clean yet efficient code. The performance of several functions of the DPC have been evaluated in real conditions, such as ADC resolution. the word length of a single acquisition is 13 bits; when measuring a constant voltage, the ADC resolution is 0.1 lsb after averaging, which is equivalent to 16 bits at 10 ms, limited by 1/f noise. But when measuring a modulated signal on a carrier, the 1/f noise disappears and the resolution is 0.0005 lsb at 100 s (corner frequency is about 0.1 Hz), which is equivalent to 23 bits. Therefore we conclude on the use of the DPC for metrology applications.
Speaker: Dr Jean Guerard (ONERA)
• 10:40 11:10
Coffee 30m
• 11:10 12:30
Space applications for analogue and mixed-signal ICs: Instrumentation
Convener: Mr Franco Bigongiari (SITAEL S.p.A:)
• 11:10
SIPHRA 16-Channel Silicon Photomultiplier Readout ASIC 20m
Speaker: Mr Hans Berge (Ideas)
• 11:30
A New Mixed ASIC for Mars Surface Application 20m
The Mars 2020 mission includes a rover designed to investigate key questions about the habitability of Mars, and assess natural resources and hazards in preparation for future human expeditions. The mission is part of NASA's Mars Exploration Program, a long-term effort of robotic exploration of the Red Planet. Mars Environmental Dynamics Analyzer (MEDA) is one of the Mars 2020 rover instruments being developed for the mission. MEDA will include a sensors suite to provide measurements of Mars near-surface atmosphere and ground temperatures, wind speed and direction, pressure and relative humidity. It includes also a sky pointing camera a set of photo-detectors for sky imaging and measurement of ultra-violet, visible and near-infrared irradiations at several bands allowing characterizing the atmospheric dust profile. MEDA wind sensor data acquisition will require the use of mixed-signal electronics to implement the front-end interface for the wind sensor transducers. These sensors are located around the Remote Sensing Mast (RSM) of the Rover. If the electronics is near to the transducers, and remotely connected to the rover’s Instrument Control Unit (ICU) through a simple serial link, the harness is notably reduced, saving a significant amount of mass. However, if the mixed-signal electronics is near to the transducers, it will be exposed to the Martian extreme temperatures, between -128ºC to +50ºC. The problem is not only the temperature range per se, but the fact that for a given sol, the temperature excursion can be of more than 70 to 100 degrees, so, when accumulated during all the mission (1.5 Martian years equivalent to 3 Earth years) all materials suffers from extreme wear-out and fatigue. The application (the ASIC) must be also demonstrated to withstand three times the mission life, that is, 3015 thermal cycles. This precludes the use of conventional space qualified semiconductors, which are typically down limited to -55ºC and not designed for withstanding those thermal cycles. To overcome this challenge, a mixed-signal ASIC with an operating temperature range of -128ºC to +110ºC has been developed. The ASIC need also to be packaged using specific materials and processes designed to counteract that fatigue. This was the case also of the previous ASIC developed for the REMS instrument on board Curiosity Rover. In this case, the REMS ASIC was tested to over 10.000 thermal cycles without showing any functional, electrical or mechanical degradation. The experience and heritage taken during the REMS ASIC development have been applied to the MEDA ASIC from the beginning to define the ASIC functionalities, the technologies and the verification program. The wind speed and direction are detected by the Wind Sensors using sigma-delta control loops. A wind sensor comprises four dice, each one with a temperature detector and a heater. The sigma-delta loops force the four dice to reach the same temperature, by applying the necessary power to each heater. Depending on the wind speed and direction, the loops will have to apply more power to one heater or another. Thus, by knowing each heater’s applied power is possible to calculate the wind speed and direction in one axis. This ASIC implements twelve control loops to interface with three wind sensors, one per axis. In addition to acquire the wind sensors information, the ASIC includes up to nine analog channels to interface other type of sensors, like thermocouples, thermopiles or resistance temperature detectors (RTDs). This enhances the ASIC front-end capabilities, expanding the applications range, and covering possible unexpected needs in MARS 2020 or in other missions. A digital state machine controls the wind sensor loops and analog acquisitions. It also communicates with the ICU through an UART interface, receiving configuration data for the different acquisition modes, and transmitting the wind sensors and analog acquisitions digitized data. Also, if a SEU is detected, it is reported to the ICU through this serial channel. MEDA WS FE ASIC main features: • 12 sigma-delta control loops for three wind sensors. 14-bit resolution for 0.5Hz and 1Hz acquisitions, and 13-bit resolution for 2Hz acquisitions. • 9 analog channels (switchable gain preamplifier + 15-bit ADC) with internal calibration, to acquire RTDs, thermocouples and/or thermopiles. • Digital machine to configure and control the wind sensor and the analog channels, with SEU detection. • 19200 baud UART with RS-422 interface. • Over-temperature protection for the ASIC and the wind sensors. • Internal housekeeping telemetries: Junction temperature and supply voltage. The ASIC design have been developed by the Instituto de Microelectronica de Sevilla (IMSE) and Crisa, using AMS 0.35 process and ECSS-Q-ST-60 methodology. We used rad hard by design libraries, pre-developed by IMSE, and fully characterized in temperature to -110ºC. ASIC prototypes (full functionality) will start testing in February 2016. Once validated, we will go for a second design to foundry iteration, to fine tune and improve functionalities and to package the ASICs using the final high reliability package. The ASIC will go through a full screening and lot qualification process afterwards.
Speaker: Mr Javier Alberola-Perales (Airbus DS - Crisa)
• 11:50
An Update on Medipix in Space and Future Plans 20m
Medipix technology in the form of Timepix chips from the Medipix2 Collaboration have been in continuous operation in LEO (Low Earth Orbit) externally (in vacuum) on satellites and internally within the ISS for over three and half years. To date no failures of the Timepix chips themselves have occurred during any of the more than 30 combined exposure-years, although there have been a few minor failures in the supporting electronics. These exposures include numerous single devices powered and readout via ISS onboard laptops, self-contained battery-powered units on the first test of NASA’s new Orion MPCV during the EFT-1 flight, as well is dedicated satellite based devices including the 5-chip LUCID (Langton Ultimate Cosmic-ray Intensity Detector) device on the UK’s TechDemoSat mission. A summary of the functional information and the data gathered from these missions are presented along with the recent evaluation of n-in-p Si sensors on both Timepix and Timepix3 chips in comparison with the baseline results using the nominal p-in-n Si sensors. Future plans include flying additional single units as radiation monitors inside the ISS and the upcoming test of the inflatable Bigelow Expandable Activity Module (BEAM) module as well as deploying a multiple Timepix stack to evaluate its potential to improve incident particle ID capability. In the longer term the primary charged particle radiation monitors to be flown on the next few flights of the Orion, called the HERA (Hybrid Electronic Radiation Assessor), is undergoing the final verification process. Evaluation of the Data-Driven Timepix3 from the Medipix3 Collaboration is underway as well, and it will be used in the verification process for the frame based Timepix and Timepix2-based devices from the Medipix2 Collaboration. The Timepix2 is in the final design process at CERN, and will be evaluated for replacement in the HERA hardware for eventual operational Orion missions. The Medipix4 Collaboration has just formed and is in the process of developing the design concept for the Timepix4 chip. The University of Houston, with support from NASA and the University, is one of the founding members of the Medipix4 Collaboration, which will hopefully ultimately provide the basis for future long term radiation monitoring and active personal dosimeter devices. With Contributions from: T. Campbell-Ricketts, S. George, A. Empl, D. Turecek, L. Tlustos, A. Bahadori, N.Stoffle, R. Rios, D. Fry, E. Semones, C. Zeilin, S. Pospisil, & J. Jakubek.
Speaker: Prof. Lawrence Pinsky (University of Houston)
• 12:10
MEDA Wind Sensor Front End ASIC 20m
The MEDA WS FE ASIC performs two main functions. On one hand, it contains an instrumentation amplifier and a 16-bits analog to digital converter (ADC) that uses a fully differential dual-slope approach, an analog multiplexer to allow the sequential conversion of 16 analog channels, and some configurable sensor-bias circuitry. This functionality aims to measure temperatures at different points in the instrument using external platinum resistors. On the other hand, the ASIC includes a number of identical heating currents and temperature control loops used to maintain a constant temperature on external silicon dies that include platinum resistors. The heat power required by each of the dies for this purpose is measured, providing an indirect measure of the wind speed (magnitude and direction). The ASIC includes a digital finite state machine (FSM) for functions control and data communications with the external control unit. Other secondary functions include internal temperature and power supply monitoring, and authomatic heaters shut-down in the event of overheating of the external dies. A power-on reset circuit has also been included, as well as the required internal voltage and current references. The die size id 5 x 5 mm approximatelly. The specified operating (ambient) temperature range is -128 to +50 ºC, the maximum ionizing radiation dose is 9Krad, and should be latch-up free up to a LET of 75 MeV-cm2/mg. It should also be robust against SEUs and SETS up to an LET of 37 MeV-cm2/mg. The controlling FSM operated on a 2.4MHz clock, provided by the external Instrument Control Unit. The communication is based on an UART. Both the external clock and data lines (Rx and Rx) use RS-422 physical layers. The interna ADC includes its specific controlling FSM that runs on a higher 50MHz internal oscillator. The ASIC is configurable in many aspects. Configuration registers include parity check for SEUs detection. It has been packaged in a 100-pins CQFP.
Speaker: Mr Servando Espejo (IMSE-CNM-CSIC / Universidad de Sevilla)
• 12:30 14:00
Lunch 1h 30m
• 14:00 15:20
Radiation-hardened technologies for analogue and mixed-signal ICs
Convener: Mr Rok Dittrich (ESA)
• 14:00
Using a Standard Commercial Process for Full Custom Rad Hard Mixed-Signal Design 20m
Speaker: Mr Volker Lück (Tesat Spacecom)
• 14:20
Radiation-Hardened SiGe BiCMOS Technologies for Analogue and Mixed-Signal ICs 20m
Speaker: Mr Maurizio Cirillo (IHP GmbH)
• 14:40
Incorporating more in-depth radiation knowledge in the DARE180U analog design kit 20m
Speaker: Mr Staf Verhaegen (imec)
• 15:00
Development of a Digital Temperature Transducer ASIC in a 28 nm FD-SOI CMOS Process for a Spaceborne Low Power Sensor Bus 20m
A geostationary satellite typically employs as many as 1000 resistive temperature sensors for its housekeeping activities. These sensors are point-to-point wired to an acquisition unit, which is often a single central interrogator system. This poses a need to develop solutions that can reduce harness complexity and weight while maintaining high reliability and keeping low cost and power consumption of the solution in mind. Digital temperature sensors fabricated as integrated circuits have become a popular choice for use in thermal management systems. The temperature sensor and the digital interface circuitry for bus-type interfaces are integrated on a single chip; thus, enabling modularity and simplicity in the system design. Implementing a sensor network in which the point-to-point connected resistive sensors are replaced with serially connected digital temperature sensors can result in a significant reduction in the amount of wiring. The selection of a suitable technology for designing such sensors is very crucial. The 28 nm Fully-Depleted Silicon on Insulator (FD-SOI) CMOS technology offers many high performance features, namely, faster switching, poly biasing, back-gate biasing for power regulation, and expected latch-up immunity. Additionally, the expected high radiation tolerance of this technology makes it suitable for the development of circuits for space applications. In this paper, we discuss the system-level requirements of a low-power digital temperature transducer application specific integrated circuit (ASIC), currently under development, in the 28 nm FD-SOI CMOS technology from STMicroelectronics. We also present our ongoing work on the chip design. The ASIC will become a part of a low power sensor bus system, to be incorporated in future geostationary satellites, where all the serially connected transducer ICs will communicate with a central interrogator module in a hybrid bus topology. The targeted temperature range of measurement is from -40ᵒC to +125ᵒC with an effective resolution of 0.1ᵒC. A measurement inaccuracy of ±0.5ᵒC is specified for the entire temperature range. On the system-level the ASIC consists of three major design blocks- a band-gap reference based temperature sensor, a sigma-delta analog-to-digital converter (ADC), and a digital serial communication interface. Additionally, circuitries for generation of the internal bias currents and low power digital calibration are included. The sigma-delta ADC has a resolution specification of 14 effective number of bits (ENOB). It is being developed in the scope of the European project called "Thin but Great Silicon to Design Objects" (THINGS2DO). Most of the analog and mixed signal blocks are powered by a 1.0 V nominal supply. For digital input/output (IO) signals a supply voltage between 1.5 V and 1.8 V is required for the IO ring. Different system-level and circuit-level techniques will be exploited to achieve low power operation of the ASIC. Design-level mitigation strategies for non-destructive single event effects (SEE) such as triplicated combinatorial logic and triplicated registers will also be employed. In line with the development of this temperature transducer ASIC, a 1st order sigma-delta modulator and its constituent operational transconductance amplifier (OTA) have been integrated as test structures on an integrated circuit (IC) called "AMBER1". The IC is realized to explore the low power features of the 28 nm FD-SOI technology. It was taped-out in November 2015 and its silicon validation is planned for the mid of 2016.
Speakers: Mr Markus Roner (OHB System AG, Munich, Germany) , Mr Pragoti Pran Bora (Fraunhofer EMFT, Munich, Germany)
• 15:20 15:50
Coffee 30m
• 15:50 16:50
Space applications for analogue and mixed-signal ICs: Radio Frequency
Convener: Hans-Dieter Herrmann (DLR)
• 15:50
Development of a Satellite TV receiver for fibre optic distribution system 20m
In this paper we highlight the design work performed by Riverbeck Ltd on the Romeo and Juliet chipset paid for by Global Invacom and the European Space Agency. Romeo and Juliet are application specific integrated circuits developed as the receiver element of a satellite TV, terrestrial TV and FM radio fibre distribution system. Fibre distribution of media signals is particularly attractive to multi-dwelling units where any TV or radio channel can be demanded by any dwelling. This demands the entire signal bandwidth be provided to all dwellings. A fibre system reduces the infrastructure cabling, is immune to electrical interference, suffers from less signal loss and can be passive split without detriment to reception. The fibre distribution transmitter (not within scope of this paper) frequency shift and modulates terrestrial radio, TV, and satellite signal using a 1310 nm semiconductor laser. Romeo and Juliet amplify the received photodiode signal, filter and frequency shift the 5GHz bandwidth to provide a set top box with the same data were it directly connected to a LNB. Romeo is a dual gain, low noise amplifier with differential outputs. Juliet provides broadband programmable RF gain, wideband continuous time filters to clean up the output spectrum, RF power detectors, 75Ω and 50Ω line driver outputs, phase locked loops to frequency shift the received spectrum, monitoring circuits and digital interfaces.
Speaker: Mr Graham Leach (Riverbeck)
• 16:10
Speaker: Dr Francesco Piazza (Saphyrion)
• 16:30
25-Gb/s/Channel VCSEL Driver and Transimpedance Amplifier Array ICs in 0.25-μm SiGe:C BiCMOS Technology for Space Applications 20m
We present monolithic VCSEL driver and transimpedance amplifier array ICs for multi-channel optical transceivers. Each IC has 3 channels and is targeted to operate at the highest data rate of 25 Gb/s/channel. Two generations of the ICs have been implemented with IHP’s 0.25-μm SiGe:C BiCMOS technology. The Gen-1 ICs contain only analog control circuits in order to focus on verification of high-speed signal path. The Gen-2 ICs are equipped with full digital control circuits with serial interface. Radiation-hardness of the digital part is achieved by adapting triple modular redundancy structures. These ICs have been developed within a European project “Multi-Gigabit, Scalable & Energy Efficient On-Board Digital Processors Employing Multi-Core, Vertical, Embedded Opto-Electronic Engines.”
Speaker: Dr Minsu Ko (IHP GmbH, Frankfurt (Oder), Germany)
• 17:30 19:00
Mayor Reception

A complimentary reception hosted by the Mayor of Göteborg will be held at the Dickson Palace. After a welcome by the Mayor, attendees and their companions will enjoy light snacks and a drink.

• 17:30
Meet in hotel lobby for 20 minute walk to the event 30m Hotel Lobby

### Hotel Lobby

• 18:00
Reception 1h Dickson Palace (Gothenburg, Sweden)

### Dickson Palace

#### Gothenburg, Sweden

• Tuesday, 14 June
• 08:30 09:00
Registration 30m

Open from 8:30 to 17:00

• 09:00 09:20
Keynote Speech
• 09:00
65nm technology developments for electronics in the LHC at CERN 20m
Speaker: Francis ANGHINOLFI (CERN)
• 09:20 10:20
Full custom digital, analogue, or mixed-signal: Data Converters (1/2)
Convener: Dr Rajan Bedi (Spacechips Ltd)
• 09:20
ESA Cosmic Vision MF ASIC and IPs Development 20m
In the radiation environment envisaged for the interplanetary mission to Jupiter named Juice, the electronic equipment will require to withstand up to 300krad of Total Ionization Dose. The availability of high performance components that can cope with that requirement is low or non-existent and for that reason ESA funded an activity to create radiation tolerant high-performance mixed-signal IPs. In the frame of the project two different ASICs where implemented: A rad-hard programmable ∑∆ modulator (CVB-001) which contains four separate ∑∆ modulator and a Rad-hard analogue front-end chip (CVC-001) which contains a Bessel Filter, a Digital to Analogue Converter, a Low Noise Amplifier and a Power amplifier. Simulation and validation results of those chips and in particular the detailed behavior of each of the IPs will be presented.
Speaker: Mr Daniel Gonzalez (Arquimea Ingenieria S.L.U)
• 09:40
First S-Band capable dual 12bit 1.5GSPS ADC in flip-chip hermetic technology 20m
In partnership with CNES, a new ADC has been developped to meet the high dynamic range as well as channel integration requirements of telecommunications payloads. It is a dual channel single core 12bit 1.5GSPS designed by e2v on ST Microelectronics BiCMOS9 technology which features 0.13µm CMOS and SiGeC NPN HBT bipolar technology (Ft/Fmax = 166/175GHz). The device is built in a hermetic flip-chip package using Aluminum Nitride material in order to reach optimized thermal performance and higher pin density. A new European Flip-Chip assembly line is being used for this device. The paper will develop the following aspects : - Target noise power ratio performance in multiple Nyquist zone. - Cross talk isolation in excess of 80dB at 2GHz. - Chosen ADC architecture. - Introduction of chained ADC synchronisation for antenna arrays (patent pending). - System benefits of S-Band high dynamic range digitization. - Mitigation of radiation effects on ST Micro BiCMOS9 technology. - Choice of package technology. - Challenges of Flip-Chip assembly at space level.
Speaker: Mr Eric Savasta (e2v)
• 10:00
High Resolution Radiation Hardened DAC in CMOS - SOI Featuring a Return - To - Zero Matrix 20m
We present a current-steering, low-noise, radiation hardened Digital-to-Analog converter, optimized to operate in the frequency range between DC and 50kHz. The DAC receives 24-bit sampled data in a synchronous serial format and converts it into a differential current analog signal. It uses a third-order multi-bit Sigma-Delta modulator, which provides superior noise and linearity performance. The embedded interpolator follows a multiple-stage architecture and consists of an FIR equiripple low-pass filter followed by two cascaded stages of Half-band equiripple filters. The last stage is a programmable SINC filter, which provides variable interpolation ratios allowing sampling rates as high as 310kHz. The system operates on a single clock domain, which is provided externally. The output current matrix features a Return-to- Zero (RTZ) technique to improve the linearity by ensuring that each elementary current source is zeroed, regardless the data value of the sample sequence. The DAC is implemented in a rad-hard 150nm CMOS-SOI process, exhibits an SNR figure of better than 108dB, and consumes 62mW of power.
• 10:20 10:50
Coffee 30m
• 10:50 11:30
Full custom digital, analogue, or mixed-signal: Data Converters (2/2)
Convener: Mr Volker Lück (Tesat Spacecom)
• 10:50
Serial I/O ADCs/DACs : The Next Giant Leap in Mixed-Signal for Space. 20m
Speaker: Dr Rajan Bedi (Spacechips Ltd.)
• 11:10
Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADC in Space 20m
Speaker: Mr Hainan Liu (Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA)
• 11:30 12:30
Exhibition: Poster and Industrial Presentations
• 11:30
"On the design of a rad-hard signal conditioning ASIC for pressure module" 1h
**European Sensor Systems** is a global developer and manufacturer of high quality sensors based on MEMS. In the course of the ESA activity 4000106328/12/NL/Cbi, European Sensor Systems is developing a “Space Qualified Family of MEMS Pressure Modules for Satellite Applications”. ![3D Model of Pressure Module][1] **Figure 1: 3D Model of Pressure Module** ESS has designed four MEMs sensors to cover the application’s pressure ranges (7, 22, 150, 310 bar) with dimensions 2×2×0.4 mm3 using X-FAB TM30P1111 technology, which is a combination of SOI, bulk and surface micro-machining process for the fabrication of capacitive pressure sensors. ESS is the IP owner and exclusive user of this process. ![Die photo of 22-bar MEMS][2] **Figure 2: Die photo of 22-bar MEMS** For interfacing with the MEMS, a custom radiation-hardened capacitive sensor signal conditioning ASIC has been designed. Based on the architecture of its commercial counterpart ASIC, ESS214 is built using X-FAB XH018 Process Design Kit, a 0.18 micron Modular Mixed Signal HV CMOS Technology. The output of the capacitance to voltage unit is converted to a 1-bit output by a second order ΣΔ modulator, which is down sampled and filtered in the digital part and finally converted to a 10-bit resolution PWM stream. The trimming of the device is performed via register programming using an I2C compatible Two-Wire Interface. A specific configuration can be written to the OTP memory once. The internal analog and digital regulator, the bandgap reference, the oscillator and the power-on reset eliminate the need of any additional components. Finally, a temperature sensor is embedded. ![ESS214 ASIC architecture and the MEMS interface][3] **Figure 3: ESS214 ASIC architecture and the MEMS interface** ![Microphotograph of the Fabricated ESS214 ASIC][4] **Figure 4: Microphotograph of the Fabricated ESS214 ASIC** In order to address the problem of SEE the Triple Module Redundancy method with voting has been adopted. This mitigation scheme uses three identical logic circuits performing the same task in parallel with corresponding outputs being compared through a majority voter circuit. The technique has been applied at the level of digital synthesis. The TMR technique has been applied to all flip-flops of the digital part. For SEL immunity in the digital part, a library of custom digital cells has been designed and characterized in house to enhance radiation tolerance. The library contains combinational, sequential and special cells (layout fillers, antenna protection cells) and was based on cells that already exist in the digital library D_CELLSL_JI3V, which contains triple-well junction isolated cells. The increase of the layout area compared to a conventional cell varies from 2x to 4x. The library has been seamlessly integrated to the IC design flow. In the analog part, all PMOS devices have been enclosed by N-type guard rings and all the NMOS devices have been enclosed by P-type guard rings. Regarding TID ESS214 is designed using standard cells. The CMOS ASIC has been tested for SEE (SEL/SEU) in the UCL cyclotron accelerator facility. The ASIC exhibited immunity to SEUs up to 32.4 MeV/(mg/cm^2) using Kr-769 and produced 2 SEUs at 62.50 MeV/(mg/cm^2) using Xe-995. The CMOS ASIC exhibited SEL immunity up to 62.5 MeV/(mg/cm^2) using Xe-995. The displacement damage test campaign is currently ongoing and results are expected soon. [1]: http://www.esenssys.com/ess/images/pressure-scaled.png [2]: http://www.esenssys.com/ess/images/mems-scaled.png [3]: http://www.esenssys.com/ess/images/ess214_func_blockdiagram-scaled.jpg [4]: http://www.esenssys.com/ess/images/asic-scaled.jpg
Speaker: Mr Theodoros Athanasopoulos (European Sensor Systems S. A)
• 11:30
Radiation Hardened by Design Pipeline Analog-to-Digital Converter Blocks in CMOS 0.18µm Technology 1h
Speakers: Prof. Hélène TAP (INP-ENSEEIHT LAAS) , Dr Olivier Bernal (INP-ENSEEIHT LAAS)
• 11:30
Si and CdTe Detector Readout ASIC in 0.35µm CMOS for Energetic Electron Spectroscopy for Taranis 1h
The compact size and power consumption of the electron energy detector instrument IDEE TARANIS requires the use of a dedicated ASIC readout circuit instead of discret devices for energy measurement. The ASIC consists of 8 CdTe, 4 regular size Si and 1 small Si detectors readout. Each channel includes a charge amplifier, a shaper, a peak detector and an 8-bit ADC. Si type channel covers the energy detection range of 70keV up to 700keV while CdTe channel covers the 300keV to 4MeV range. For a 40-pF detector parasitic capacitances, low noise performances are achieved: 3120e- for Si type channels and 2335e- for CdTe type channels. Low power performance of 2mW at 650-kHz frequency per Si channel and 2.9mW at 40-kHz per CdTe channel is achieved. While both type of channel share a similar design, CdTe type channel analog front end had to include a pole zero cancellation in order to achieve the required frequency of operation. The ASIC has been tested in standalone as well as interfaced with the detectors. Finally, the ASIC has been qualified with a heavy ion test. The ASIC has been implemented in AMS 0.35µm HV CMOS technology.
Speakers: Mr Olivier Bernal (ENSEEIHT/INP - LAAS/CNRS) , Mrs king wah wong (CNRS - IRAP)
• 11:30
SOI CMOS Frequency Synthesizer for Flexible Communications Payloads 1h
Speaker: Dr Seong-Mo Moon (Electronics and Telecommunications Research Institute (ETRI))
• 11:30
Status of the GR718B Product - a Radiation-Tolerant 18x SpaceWire Router for Space Applications 1h
GR718B is a radiation tolerant 18 port standalone SpaceWire router component that has been developed by Cobham Gaisler together with imec (BE), in an activity initiated by the European Space Agency under ESTEC contract 4000105402/12/NL/CBi.No. All ports are capable of operating in 200 Mbit/s. UART and JTAG interfaces, that gives access to the on-chip bus, are provided for configuration and debugging. SPI and GPIO interfaces are accessible through the configuration port, which allows SPI devices to be accessed and general purpose signaling to be performed through RMAP commands. In addition to the mandatory features in the current ECSS SpaceWire standard, GR718B supports group adaptive routing for path addresses, and packet distribution. It also includes support for the incoming SpaceWire standard revision 1 (ECSS-E-ST-50-12C Rev.1), the SpaceWire-D protocol, and the SpaceWire Plug-and-Play protocol currently being developed for ECSS. The technology used is UMC´s CMOS 180 nm, using the DARE library from imec, and the package is a 256 leads CQFP. The GR718B router is expected to withstand 300krad(Si) and is single event latch-up immune for linear energy transfer values above 118 MeVcm2/mg. The GR718B is currently being qualified for space applications following an ESCC9000 lot validation approach. Flight units will be available from January 2017. Prototypes and evaluation boards are already available.
Speaker: Mr Fredrik Johansson (Cobham Gaisler AB)
• 12:30 14:00
Lunch 1h 30m
• 14:00 14:40
Radiation-hardened technologies for analogue and mixed-signal ICs: High Voltage
Convener: Mr Olle Martinsson (Ruag)
• 14:00
Challenges of Designing a Radiation Tolerant Motion Control System on Chip 20m
Speaker: Mr Bruce Ferguson (Microsemi)
• 14:20
RADIATION HARDENED HIGH-VOLTAGE AND MIXED-SIGNAL IP WITH DARE TECHNOLOGY 20m
Recent trends show the growing need for more analog, mixed-signal and high-voltage IP to enhance the intelligence and reduce the cost of satellites. This paper presents the set of radiation hard, mixed-signal and high-voltage IP that is part of the imec DARE solution and that is developed in UMC 0.18um, XFAB XH018 and On Semiconductor i3t80 technology. The IP is conceived to enable rad-hard SoC developments and consists of ADCs, PLLs, clocks, linear regulators, bandgap references with current reference and temperature sensors, high-voltage DCDC converters to convert the satellite main supply to analog and digital on-chip voltages and several high-power and high-voltage switches and drivers for a.o. HPC (high-power commands). The IP is versatile to be useful in a myriad of applications and is part of the DARE platform. The IP in UMC 0.18um has been successfully silicon proven and radiation tested. First-time-right radiation hardness is achieved through a proprietary under-radiation simulation approach developed by ICsense and elaborated in this paper.
Speaker: Dr Bram De Muer (ICsense)
• 14:40 15:20
Full custom digital, analogue, or mixed-signal: Receivers and Transmitters (1/2)
Convener: Mr Steven Redant (IMEC)
• 14:40
Octal LVDS Repeater Test Results 20m
The purpose of this paper is to present the electrical and radiation results of the tests performed on the LVDS Octal repeater developed by ARQRUIMEA in the frame of ESA’s and ECI’s European LVDS Driver Development intended to be used in space applications and built in IHP’s 0.25-um BiCMOS process technology. The key features of the octal LVDS repeater include cold sparing, more than 250MHz signaling rate per channel allowing more than 500Mbps transfer rates over SpiceWire, 3.3V single power supply, low channel to channel skew, TRI-state output control, extended common mode on LVDS receivers and t ESD tolerance up to of 8kV for human body model The Octal LVDS repeater has been tested up to 300Krad without important degradation. Additionally, the devices have shown no sensitivity to Latch-up up to the maximum tested LET of 62.5 MeV cm2/mg. The octal repeater is not sensitive to SET or SEU up to 20 MeV cm2/mg. At higher 62.5 MeV cm2/mg 15 bit errors were detected after 1012 transmitted bits.
Speaker: Mr Jesús López (Arquimea Ingeniería S.L.U)
• 15:00
SEPHY: An Ethernet Physical Layer Transceiver for Space 20m
Speakers: Mr Daniel Gonzalez (Arquimea Ingenieria S.L.U) , Mr Jesús López (Arquimea Ingenería S.L.U)
• 15:20 15:50
Coffee 30m
• 15:50 17:10
Full custom digital, analogue, or mixed-signal: Receivers and Transmitters (2/2)
Convener: Steven Redant (IMEC)
• 15:50
A 2.56 Gbps Radiation Hardened LVDS/SLVS Receiver in 65 nm CMOS 20m
Many of today's applications require high precision time-domain signal processing circuits like particle detectors in high-energy physics experiments such as the CMS and ATLAS experiments at the Large Hadron Collider (LHC) in CERN or laser-ranging sensors. The key information of these applications is contained in the timing difference between multiple signals or events. This timing information is usually converted to binary data using time to digital converters (TDC). In large and/or complex systems however, the distance between the detector/event generator and the TDC can become rather large, calling for a highly time accurate, long distance, transfer of these signals. Many applications now use Low Voltage Differential Signaling (LVDS) and Scalable Low Voltage Signaling (SLVS) for data transmission because of its robustness to interferences, low power consumption and high speed. The SLVS standard is comparable to the LVDS standard, with the difference of a 200 mV common mode voltage and 200 mV voltage swing instead of 1.2 V common mode and 400 mV swing. For data transmission applications, the regenerative nature of the receiver allows some tolerance to jitter provided the bit error rate remains low. However, in the envisaged sub-nanosecond timing applications, jitter is the major impairment to the performance of the system. When an LVDS/SLVS receiver is used in the signal path between the event generator circuit and the TDC, any time distortion introduced by the receiver, will cause a time measurement error and consequently will lower the system resolution. To allow an accurate time measurement, the propagation delay of all the edges, at the output of the LVDS/SLVS receiver, must be the same. This paper focuses on the design of a radiation hardened by design LVDS/SLVS receiver which can be used in high resolution time measurement applications. This design uses a NMOS input pair, single ended output op amp structure where the output currents can be tuned in order to achieve an equal propagation delay between the rising and falling edges at the output of the receiver. In radiation environments, the total ionizing dose (TID) will change the gain/propagation delay of the receiver, due to shifts in the threshold voltage and degradation of the charge carrier mobility. This will introduce a propagation delay mismatch between the rising and falling output edges. To compensate this mismatch, a replica receiver is added which is capable of measuring the difference in propagation delay between the two edges. When the propagation delays of the rising and falling edges are equal, an ideal clock at the input of this replica receiver must generate a clock signal at the output with a duty cycle of 50 % and a common mode voltage of $V_{DD}/2$. Any mismatch in this duty cycle, caused by the TID effects, will be measured by the integrating feedback loop and will be used to adjust the currents through the receiver in order to equalize the propagation delays of the output rising and falling edges. The proposed receiver is designed and simulated using a commercial 65 nm CMOS technology. This technology has a power supply of 1.2 V which is identical to the common mode voltage of an LVDS signal. In this design, for an optimal use of the NMOS input pair receiver, the common mode voltage of the input signals must be between $\pm$ 0.5 V - 1 V. This is fine for ad-hoc systems, like the CMS and ALTAS detectors at CERN, which don't need to communicate with off-the-shelve LVDS modules, and so can freely choose the common mode level. Nevertheless, the proposed technique is easily scalable to I/O devices or other technologies with a larger power supply for full LVDS compatibility. Additionally, a PMOS input pair receiver is designed which is able to receive low common mode voltage and SLVS signals. The proposed receiver is capable of supporting event rates equivalent to a 2.56 Gbps data rate with less than 400 fs output RMS jitter and 500 $\mu$W power consumption from a 1.2 V power supply.
Speaker: Mr Bram Faes (KU Leuven)
• 16:10
European LVDS Development - current status 20m
The integration of a dual LVDS receiver and transmitter into one package, meeting the space radiation, cold-sparing and capable of handling large common mode signals, is a necessity to meet the increasing demand for robust SpaceWire communication in satellites. In the frame of an ESA activity under the European Component Initiative (ECI) program, Cobham-Gaisler has undertaken the development of such LVDS transceiver, ideally suited for SpaceWire links, to complement its product range of SpaceWire products. The scope of the LVDS transceiver development will be presented together with the architecture of the LVDS transceiver. The specific implementation issues pertinent to the reliable operation of the SpaceWire link operation in space like the receiver input hysteresis, embedded active fail-safe circuitry, cold-spare and 8kV ESD protected IO's in addition to applied radiation mitigation methodology will be discussed. Finally the relevant prototype electrical and radiation test results will be presented.
Speaker: Mr Fredrik Sturesson (Cobham Gaisler AB)
• 16:30
Radiation Tolerant CAN Transceiver for Space 20m
The severe -2V to 7V common-mode and -3V to 16V failure tolerance requirements of the CAN bus have restricted its implementation to high-voltage processes with transistors tolerant to voltages above 16V. This paper demonstrates for the first time that a CAN transceiver can also be realized with standard 3.3V 350nm CMOS double and triple well devices available in Mixed Mode 180nm CMOS technologies. This leads to lower power consumption, lower bus port capacitances and facilitates integration with the CAN controller and large digital circuits, while for space provides higher radiation tolerance.
Speaker: Dr Richard Jansen (ESA)
• 17:30 22:15
Cruise of the Göteborg Waterways

A local guide will describe the sights of the city with seating available below and on the deck of the M/S St Erik, (named after Erik IX; King of Sweden late 1150) docked at the Göteborg Harbor - bring your camera!

• 17:30
Meet in the hotel lobby to walk to the harbor 15m Gothenburg, Sweden

#### Gothenburg, Sweden

• 17:45
Arrive at Göteborg Harbor and board M/S St Erik 15m Gothenburg, Sweden

#### Gothenburg, Sweden

• 18:00
Cruise begins 30m M/S St Erik

#### M/S St Erik

• 18:30
Departure 1h 15m Cruise (Gothenburg, Sweden)

### Cruise

#### Gothenburg, Sweden

Depart boat for Nya Älvsborgs Fästning tour. Your arrival at Nya Älvsborgs Fästning (Fort) will be welcomed with a cannon blast. The fortress on Kyrkogårdsholmen (Cemetary Island) at the entrance of Göteborg harbor, began construction in 1653.

• 19:45
Cruise 2h 15m M/S St Erik (Gothenburg, Sweden)

### M/S St Erik

#### Gothenburg, Sweden

Reboard the M/S St Erik and cruise to the River Café for dinner

• 22:00

#### Gothenburg, Sweden

• Wednesday, 15 June
• 08:30 09:00
Registration 30m

Open from 8:30 to 17:00

• 09:00 09:20
Keynote Speech
• 09:00
First Telecom Application of Digital and Mixed Component Developments:65nm ASIC and Data Converters 20m
First we will give an overview of Digital Transparent Processor (DTP) development in the frame of FAST project. The DTP is a key element of TAS SpaceFlex processor. DTP development is targeting both commercial and defense satellites. New generation of DTP is able to address high bandwidth, with high capacity with a cost decreases in mass, power consumption and volume per GHz. Then we will report on the key technologies for DTP. It’s about first 65nm ASIC from TAS-Atmel-STMicroelectronics and E2V data converters. To address the need of high integration, low power consumption, 65nm ASIC offer was developed by ATMEL and STMicroelectronics with CNES and ESA support. This offer incorporates HSSL link. First ASIC was designed by TAS and called VT65. VT65 ASIC was manufactured by Atmel, ST and E2V, using flip-chip technology. VT65 tests are now completed and results are in line with the target. With CNES support, E2V has designed high speed, large input bandwidth, low power data converters. EV12AD550 ADC ESCC evaluation is started and first test results will be presented, showing very good performances. EV12DS130A DAC is now used in Telecom space programs. To conclude DTP is a high tech product with high innovation, for drastically enhanced performances, thanks to a constructive collaboration between all the FAST partners, Telecoms, Technologists, Components engineers and Manufacturers.
Speaker: Mrs Florence Malou (CNES)
• 09:20 10:00
Evaluation and qualification of full custom ICs for space applications
Convener: Mrs Florence Malou (CNES)
• 09:20
Design Methodology for mixed signal ASIC with prequalified Analog IPs for space applications 20m
Mixed Analog / Digital System on Chip are increasing drastically in space equipment to reduce cost, power and dimensions and to improve performances. The challenge for mixed SoC is to get a qualified product without heavy SEE or TID testing. As for a digital library, analogue cells and their combinations, High voltage LDMOS, regulators (to allow single supply) and latch-up protections must be “pre-qualified”. The qualification of IOs and digital is done by using a Standard Evaluation Circuit covering at least half of the maximum of transistor of an ASIC. For the analog part all blocks must be validated. In addition, in order to check the “integrability” of the building blocks towards the elaboration of a complex space-adequate System-on_Chip, a complex function will be realized embedding all individual analog cells and a digital block embedded as an analog cell. During the realization of this complex function emphasis is given to the observability and testability of the individual building blocks. For each new analog cell the same process must be conducted. The study will continue by determining the observability of the analog nodes and specifically the eventual propagation of Single Event Transient. This study is conducted with support of ESA and CNES and with European industrial partners. ATMEL ATMX150RHA offers a wide range of capabilities to enlarge the SoC integration: digital integration up to 20M gates, NVM, analogue, 3Gbit serial interface, N and P deep well, Deep Trench to isolate blocks, handle Wafer contact, 1.8V digital core, 3V, 5V, 15V and high voltage up to 60V. Mixing power, high voltage and high speed on a single chip needs adequate packaging technology, large die and small die must be handled by different packaging solutions: double pad ring, flipchip, Au bonding, Al bonding. ATMEL can base the qualification for space requirements on standard process used in high volume. It ensures longer process lifetime and stability, as well as lower access cost. Same advantages applies to probe, assembly and final test. A mixed Standard Evaluation Circuit is under definition in order to check the “integrability” and “space testability and observability” of the building blocks. The flow and the rules for integration of analogue cells coming from multiple suppliers will be clearly defined and qualified. Key words: mixed Soc, embedded NVM, high voltage LDMOS, mixed MPU, mixed MCU
Speaker: Mr Bernard BANCELIN (ATMEL NANTES S.A.S.)
• 09:40
Approval Process of an ESCC Qualified ASIC Supply Chain based on a Mixed-Signal IP Library 20m
A fast and reliable development of a Rad Hard Space product benefits on a dynamic and efficient way of an ASIC design and supply chain. Design and qualification of a new ASIC is associated with a long development phase. Using an ESCC qualified IP library for the ASIC can reduce this development phase significantly and lowers the costs of the product. This supply chain resolves the trade-off between a full custom design with all associated qualification steps and a semi optimized product based on standard ICs. IMST and TESAT Spacecom are currently working in a DLR funded R&D project to built up such an ASIC supply chain that will be offered by IMST after approval by ESCC consortium. Completion of this project is planned for Q1 2017. A first publication of this ASIC supply chain establishment has been given on the AMICSA 2014 in CERN with the title: 180nm CMOS Mixed-Signal Radiation Hard Library as base for a full ASIC supply chain Now an update will be given on the current status of this project with measurement results including TID and SEE evaluation. The designed Library elements will be presented and an overview of the supply chain will be given with all supported technology features, package choices and the design flow information. The radiation hardened library designed by IMST, called HARD Library (HARD= Hard Against Radiation Design) is built on the XH018 180 nm CMOS technology from XFAB. It supports I/O cells for 3.3 V and 5 V supply as well as level shifter I/Os for a negative supply voltage of -5 V on the ASIC. The other IPs are specified with the intention to cover a wide range of applications. The IP library contains data converters, biasing cells, memory modules, a reconfigurable opamp, LVDS driver and receiver, SPI interface, OTP cells, clk PLL, oscillators and special I/Os with cold spare functionality. A ceramic quad lead frame package family has been developed for the supply chain with different pin counts from 32 up to 256, supporting die sizes from 1.5 X 1.5 mm^2 for the smallest package up to 10 X 10 mm^2 for the largest package. Two main design flows are targeted: One is a turn-key design by IMST based on customer requirements, while the other flow assists a co-design with the customer where the customer is allowed to provide encrypted VHDL codes. In the latter case IMST is creating the netlist with selected digital standard cells and implements TMR structures in order to guaranty a Rad Hard design. Analog features are handled by IMST using the IP library. On either case IMST delivers a tested, qualified and assembled Rad Hard ASIC.
Speaker: Mr Jan Steinkamp (IMST GmbH)
• 10:00 10:40
Radiation tests of analogue and mixed-signal ICs
Convener: Mr Fredrik Sturesson (Cobham Gaisler)
• 10:00
The pros and cons of in situ testing - going beyond the test standards 20m
Speaker: Dr Sharp Richard (Cobham RAD Solutions)
• 10:20
Total Ionizing Dose Testing of Solid State Power Amplifiers 20m
Radiation testing of in-house developed GaAs-based Solid State Power Amplifiers (SSPAs) operating at super high frequencies (SHF) has been performed with a Co-60 source. GaAs-based electronic components are considered to be generally immune against Total Ionizing Dose (TID). Test results are presented here to quantify residual performance degradations of these SSPAs at various total ionizing doses and other extreme environmental conditions.
Speaker: Prof. Melahat Bilge DEMIRKOZ (Middle East Technical University)
• 10:40 11:10
Coffee 30m
• 11:10 12:10
Radiation Effects on analogue and mixed-signal ICs
Convener: Mr Fredrik Sturesson (Cobham Gaisler)
• 11:10
In a radiative environment, when a particle with a given LET (Linear energy transfer in MeV.cm²/mg) hits the substrate of a circuit, it creates electron-hole pairs along its braking track; this causes current injections between junctions and consequently upsets node voltages. These transients are called SETs (Single Event Transient). For digital circuits like the FPGA core, a SET corrupts the data as it makes a sequential bit to flip. Due to technology down-sizing and reduction of supply voltage, circuits become even more sensitive to radiation. This work is implemented in ST CMOS 65nm process. In order to improve the reliability of our FPGA, dedicated to the applications in radiative environments, our full custom library have been simulated using IROC software (TFIT). TFIT calculates the currents injections and simulates their effect by running SPICE simulation. During the hardening process, two kinds of studies were carried out: • The Single Event Upsets (SEU) that is a direct upset of a sequential logic (configuration of SRAM and Digital Flip Flop (DFF)). For SRAM, the cell under study with the smallest capacitive load was considered as the worst case. • The Single Event Transient (SET) in the clock and reset networks can have 2 effects: Jitters that occurs at the clock edge and the glitches that occurs between the clock edges. These effects can make a bit error to propagate in DFF. The design efforts are put on the glitches considering a static clock. Thus we are in a worst case situation in which jitters are replaced by glitches. Moreover, in our designs, Jitter occurs rarely compared to the glitches. This is because minimum period of a clock is 5ns whereas the SET duration is less than 300ps for a LET less than 58 MeV.cm²/mg in normal incidence. Besides, an upset on reset signal can reset a DFF storing “1”. The smallest clock glitch to write in DFF is 150ps. Hence the glitches longer than 150ps are considered as a SET error. No capacitive and resistive load is added in order to simulate the worst case of the cross section. SEU and SET effects are studied and radiation hardening is performed on all the library cells that are sensitive to these effects: • SEU in configuration memory: configuration memory of our SRAM based FPGA; they are very critical and require a high level of hardening. • SET on clock/reset buffer and matrix: they propagate clock and asynchronous or synchronous reset into the circuit with a low skew. • SEU/SET Digital Flip Flop: user register. In order to improve the reliability, design optimization are made on structure and layout by calculating upset current with TFIT and running SPICE simulation for different positions (step 50nm) and incidence angles (3 tilt angles x 8 rotation angles). TFIT software give an estimation of the normal and average angular cross sections. The cross section represents the whole sensitive area (normal to the incidence) through which a particle impact causes an SEU/SET. Thus the cross section of the structures is reduced by alternately improving layout and running simulation under 1.08V, lowest supply voltage, typical corner and 25°C. The layout is optimized by putting more distance between sensitive nodes and by bringing the tap closer to them. The results of worst cross section among the different states for the different cell show a great improvement of the radiation hardness.
Speaker: Mr Quentin CROENNE (Nanoxplore)
• 11:30
Radiation Prediction Tool Dedicated to Analyzing and Hardening by Design readout circuits of photonic ICs 20m
Speaker: Mr Laurent Artola (ONERA)
• 11:50
Single Event Simulation and Error Rate Prediction for Space Electronics in Advanced Semiconductor Technologies 20m
Abstract: The effect of a single event in today’s advanced semiconductor technology is no longer restricted to a single circuit node, and can depend strongly on layout details, on the angle of the ion, and on the response of the circuit during the charge collection. In order to catch weak spots in circuits and layouts, and to get reliable predictions for space error rates, it is important to have a possibility to model the circuit designs with a full (and correct) description of the layout, of direction of the ion, and of the time profile of the charge collection. This talk discusses simulation techniques which makes this possible, while still being fast enough to be used to generate full cross-section maps and error rate predictions for different radiation environments. Application examples from advanced FinFET technologies (logic) and bulk technologies (including analog and oscillatory circuits) will be presented along with comparisons to measured single event data.
Speaker: Mr Klas Lilja (Robust Chip)
• 12:10 12:30
Wrap Up
• 12:30 14:00
Lunch 1h 30m
• 14:00 14:15
ESA DSP Day 2016 Introduction
Convener: Dr Roland Trautner (ESA/ESTEC)
• 14:00
ESA DSP Day 2016 - Day 1 Introduction 15m
Speaker: Dr Roland Trautner (ESA/ESTEC)
• 14:45 15:45
Convener: Mr Sandi Habinc (Aeroflex Gaisler AB)
• 14:45
Scalable Sensor Data Processor: Architecture and Development Status 30m
Speaker: Mr Ricardo Pinto (Thales Alenia Space)
• 15:15
RC64: High Performance Rad-Hard Manycore DSP 30m
Speaker: Prof. Ran Ginosar (Ramon Chips)
• 15:45 16:00
Coffee break
• 16:00 17:00
Session 2: Test, Verification and Qualification of DSP Chips
Convener: Mr Boris Glass (ESA)
• 16:00
ESCC Qualification of Space Components - Schemes and New Opportunities 30m
Speaker: Mr Fernando Martinez (ESA)
• 16:30
Scalable Sensor Data Processor: Testing and Validation 30m
Speaker: Mr Ricardo Pinto (Thales Alenia Space)
• 17:00 18:00
Session 3: COTS based DSP Systems and Boards
Convener: Dr Roland Trautner (ESA/ESTEC)
• 17:00
High Performance COTS based Computer for Regenerative Telecom Payloads 30m
Speaker: Mr Olivier NOTEBAERT (Airbus Defence and Space)
• 17:30
SpaceWire and SpaceFibre Interconnect for High Performance DSPs 30m
STAR-Dundee with the University of Dundee has recently designed several high performance DSP units each using SpaceWire or SpaceFibre interfaces to provide an input/output performance in-line with the capabilities of the specific DSP processor. The first DSP unit is for the High Processing Power Digital Signal Processor (HPPDSP) project, which is an ESA funded project led by AirbusDS with STAR-Dundee Ltd and CG Space. It aims to build a high performance, programmable DSP processor suitable for spaceflight applications. STAR-Dundee was responsible for the hardware, FPGA and low level software development. The HPPDSP is designed around the TI TMS320C6727B processor which is available as a space qualified part. The DSP processor connects to external SDRAM via its EMIF (external memory interface) bus. Peripherals that are directly controlled by the DSP processor are attached to the EMIF bus via an FPGA. Other peripherals that are able to access DSP memory and registers in parallel with the DSP processor are attached to the UHPI (Universal Host Processor Interface) bus of the DSP processor via the FPGA. A board has been designed incorporating the TMS320C6727 processor, SDRAM memory and a Xilinx Virtex 4 FPGA. The FPGA includes EDAC for the SDRAM memory, memory management, SpaceFibre and SpaceWire interfaces, and other general purpose interfaces. A high sample rate ADC/DAC interface is also included. The second DSP project is a high performance FFT processor for a THz Radiometer. Implemented in various FPGA technologies this Wideband Spectrometer (WBS) is able to perform 2k point complex FFTs at a sample rate of around 2.4 Gsamples/s in radiation tolerant technology, a total processing power of more than 200 GOPS. Each FFT board processes a 2 GHz wide band to a resolution of around 3 MHz. SpaceWire is used to gather the data from several of these spectrum analysers to handle up to 12 GHz bandwidth. The third DSP project is the Ramon Chips RC64 Many Core DSP processor, where STAR-Dundee provided the SpaceWire and SpaceFibre technology for this very powerful programmable DSP processor. The paper will describe the HPPDSP architecture, the FPGA design and the board design. It will give an overview of the WBS system and present the latest implementation of this high performance DSP system. A brief summary of the RC64 processor will be provided. In each case the role of SpaceWire and SpaceFibre in the different systems will be described.
Speaker: Prof. Steve Parkes (University of Dundee)
• 18:00 18:15
ESA DSP Day - Day 1 Oral Sessions Wrap-up and Poster Session Introduction / Day 2 Logistics
• 18:15 19:30
Session 4: DSP Day Reception and Poster Session
• 18:15
Characterization and qualification of microcontrollers and DSPs in extreme temperatures 1h 15m
**1.Introduction** Microcontrollers and DSPs are key components of embedded systems for most applications (space, avionics, industry…). The reliability of these components has to be asserted to ensure the correct working of the system for the duration of its mission while preserving its performances. Designers are currently greatly tempted to use commercial components for their applications; they are easier to use and buy while providing higher calculation performances. However, these components generally have not been tested in extreme environments. From these facts, it seems mandatory to consider the importance of testing microcontrollers and DSPs before employing them in space applications, or any other application that comes with an extreme environment. That is the reason why the electrical test and reliability team of THALES Communications & Security worked on the subject. This document summarizes test methods and shows some results in regards to testing and qualification of microcontrollers and DSPs in high temperatures. Results described in this abstract have been observed by testing ARM M0 & M4 microcontrollers for industrial application. **2.Characterization** Characterization tests were performed on a few components to quantify the drift of their performance and behavior relatively to temperature. In order to obtain the most precise measurements, the part under test is mounted on a daughter board plugged into an ATE (Automatic Test Equipment). High temperature environment is achieved using an air stream temperature forcing system (see picture below). http://hpics.li/c5ac942 *Figure 1: Mutest ATE with ThermoStream to characterize components* A firmware including several test scenarios is programmed into the device. The ATE then orders the component to launch perform the various test scenarios with voltage, clock frequency, and temperature variations. More exactly, the following parameters can be tested: - Core functionalities (boot sequence, multi-core communication, voltage supervisor, interruption) - Clock structure (internal clocks, external clocks, PLL, timers) · Processing modules (ALU, FPU, TMU) - Internal memory (volatile and nonvolatile, user and program memory) - Peripheral communication modules (ex: UART, SPI, I2C, CAN, Ethernet) - Analog blocks (ADC, DAC, comparator, PWM) - Operating and low power consumption modes - I/O characteristics (leakage current, input and output voltage) According to the tested device, various parameters evolve over temperature, the most noticeable one being current consumption (see the chart below): http://hpics.li/d95d930 *Figure 2: Current consumption of tested microcontroller in low power mode over temperature* This first chart shows the current consumption of a microcontroller in a low power mode according to voltage (2.5 or 3.3V) setting and temperature. The low power mode displays an obvious temperature limit to its use. Indeed, from 210°C @2.5V and 215°C @3.3V current consumption is the same as in normal mode. This result also highlights the need for a higher voltage supply to function as temperature increases. Nevertheless, a different test performed on another component, points out the decrease of the maximal operating voltage supply as temperature increases. The root cause of this would be the decrease of the output voltage provided by the internal regulator when current consumption gets too high (higher current consumption as temperature increases). The application report “Understanding the Terms and Definitions of LDO Voltage” [2] mentions this particular behavior relative to voltage regulators. http://hpics.li/e113d3a *Figure 3: Regulator output voltage vs output current draw* This phenomenon can be observed when testing the ADC module by measuring a stable input (VCC/2) while using the internal voltage regulator as voltage reference. http://hpics.li/3e86bfb *Figure 4: ADC measurements with internal reference* On the other hand, performing the same test with an external reference gives stable result up to at least 190°C. In the case of the internal reference, the ADC output code positive data at high temperature comes from a negative drift of the voltage reference. What’s more, the higher the voltage supply, the higher the ADC code gets. It goes without saying that these examples are only a few among other parameters to show both functional and parametric behavior changes along with temperature. **3.Qualification** Assessing the functional configurations of the device under test is one thing, ascertaining its ability to remain in working conditions for the duration of its application is yet another. As for the characterization, several scenarios are implemented into the embedded firmware. A digital sequencer in the cold side continuously and sequentially calls all scenarios executed by devices under test in the hot side. http://hpics.li/88459a7 *Figure 5: SANSA architecture* This homemade system is named SANSA: Solution to Activate Numerical Systems for Ageing. Its aim is to simulate as well as possible the working conditions of the device under test (extreme environment for thousands of hours). Such a testing methodology quantifies drifts over time of both parametric and functional performances of the tested parts. A critical parameter to monitor during such an ageing test is the complete retention of the program memory embedded in the DSP. Data corruption might reach error rat that cannot be compensated by correction algorithms (ECC). The JEDEC standard JESD218 [3] states the decrease in retention time capabilities of a typical FLASH memory in regards to temperature by using models from the JEDEC standard JEP122G [4]. For example, the Arrhenius equation can be used to compute the acceleration factor due to a temperature increase, and to have an estimation of the retention degradation caused by temperature. **4.Conclusion** This document summarizes test methods to ensure performance and reliability of a microcontroller or a DSP in high temperatures, and shows some test results. In addition, this methodology can also be applied to test devices’ behaviors in a radiation environment, especially to test internal memory resiliency. To finish, this qualification process can just as well be implemented to qualify FPGA devices for space applications, and to compare their performances with DSPs’. **Reference** *[1] “Extreme Environment Electronics”, John D. Cressler, Alan Mantooth* *[2] “SLVA079: Understanding the Terms and Definitions of LDO Voltage Regulators”, Bang S. Lee, Texas Instrument* *[3] “JEDEC standard JESD218: Solid-State Drive (SSD) Requirements and Endurance Test Method”* *[4] “JEDEC standard JEP122G: Failure Mechanisms and Models for Semiconductor Devices”*
Speaker: Mr Flavien DOZOLME (THALES Communications & Security)
• 18:15
DVB-S2 Software Defined Radio Modem on the RC64 Manycore DSP 1h 15m
Speaker: Prof. Ran Ginosar (Ramon Chips)
• 18:15
Open-Source Instrument Flight Software for CHEOPS 1h 15m
Speaker: Dr Roland Ottensamer (University of Vienna)
• 18:15
Radiation Intelligent Memory Controller IP Core 1h 15m
Speakers: Mr Charles Sellier (3D PLUS) , Mr Pierre-Xiao WANG (3D PLUS)
• Thursday, 16 June
• 08:30 09:00
Registration 30m

Open from 8:30 to 12:00

• 09:00 09:05
ESA DSP Day - Day 2 Introduction
Convener: Dr Roland Trautner (ESA/ESTEC)
• 09:00
ESA DSP Day 2016 - Day 2 Introduction 5m
Speaker: Dr Roland Trautner (ESA/ESTEC)
• 09:05 11:05
Session 5: DSP Software and Applications
Convener: Mr Olivier NOTEBAERT (Airbus Defence and Space)
• 09:05
Speaker: Dr Javier Jalle (Cobham Gaisler)
• 09:35
A Lightweight Operating System for the SSDP 30m
Speaker: Mr Armin Luntzer (University of Vienna)
• 10:05
High-performance DSP for onboard image processing 30m
Speaker: Mr Jamin Naghmouchi (TU Braunschweig)
• 10:35
Space Debris Detection on the HPDP, a Coarse-Grained Reconfigurable Array Architecture for Space 30m
Speaker: Mr Diego Suarez (Technische Universität München)
• 11:05 11:30
Coffee break
• 11:30 12:30
Session 6: IP Cores, FPGAs, and their Synergies with DSPs
Convener: Mr Jan Andersson (Aeroflex Gaisler)
• 11:30
Multi-core DSP sub-system IP 30m
**Architecture** The multi-core DSP sub-system comprises the following key building blocks: • The Xentium® is a programmable high-performance DSP processor core that is efficient and offers high-precision; • Network-on-Chip (NoC) technology provides sufficient bandwidth, flexibility and predictability which are required for interconnecting DSP cores and I/O interfaces in streaming DSP applications. The presented multi-core DSP sub-system consists of programmable fixed-point (and floating-point in the future) DSP cores that are connected by a NoC. After initialization by the host processor, the multi-core DSP sub-system will autonomously run compute-intensive DSP functions. **Network-on-Chip** The NoC provides the bandwidth and flexibility that is required for streaming DSP applications. The communication bandwidth in a NoC scales with the number of cores. In conventional bus architectures, additional processors share the original bandwidth and will eventually create a bottleneck. A NoC ensures predictable performance due to its point-to-point connections, in contrast to the unpredictability of a shared bus. Moreover, NoCs allow disabling inactive parts of the network, which is essential for energy-efficiency and dependability. Using transparent I/O interfaces it is possible to extend the NoC across the chip boundaries. Several I/O interfaces are available on the multi-core DSP architecture, such as SpaceWire bridge interfaces, bridges to external Analog-to-Digital Convertor (ADC) and Digital-to-Analog Convertor (DAC) devices. All NoC interfaces employ memory-mapped communication. **Xentium DSP** The Xentium is a programmable high-performance 32/40-bit fixed-point DSP core for inclusion in multi-core systems-on-chip. High-performance is achieved by exploiting instruction level parallelism using parallel execution slots. The Very Long Instruction Word (VLIW) architecture of the Xentium features 10 parallel execution slots and includes support for Single Instruction Multiple Data (SIMD) and zero-overhead loops. The Xentium is designed to meet the following objectives: high-performance, optimized energy profile, easily programmable and memory mapped I/O. **Xentium DSP – Datapath** The Xentium datapath contains parallel execution units and register files. The different execution units can all perform 32-bit scalar and vector operations. For vector operations the operands are interpreted as 2-element vectors. The elements of these vectors are the low and high half-word (16-bit) parts of a 32-bit word. In addition several units can perform 40-bit scalar operations for improved accuracy. All operations can be executed conditionally. The Xentium datapath provides powerful processing performance: 4 16-bit MACs per processor clock cycle or 2 32-bit MACs per cycle or 2 16-bit complex MACs per cycle. Currently, the fixed-point Xentium datapath is being upgraded to support floating-point operations as well. **Xentium DSP – Tightly-coupled Data Memory** Private local memories are available y is available at the Xentium DSP. The tightly-coupled data memory is organized in parallel memory banks to allow simultaneous access by different resources. The data memory can be simultaneously accessed by the Xentium core as well as other cores connected through the NoC. By default the data memory in the Xentium tile is organized in 4 banks of 4 kBytes each, implemented using SRAM cells. The size of the memory banks is parametrizable at design-time. **Software Development and Debugging** The software development for the Xentium is supported by a C compiler, an assembler, a linker, a simulator, a debugger, and a number of utilities. The compiler translates C source code into Xentium assembly language source code. In order to ease the software development on the multi-core DSP architecture, the architecture has been equipped with multi-core DSP debug infrastructure. The Xentium DSP cores have integrated hardware debug support to intrusively debug all registers in the Xentium datapath. Also, a cross-trigger unit allows the debugging of multiple Xentium cores in parallel. The debug infrastructure interfaces with standard GDB debug tools.
Speaker: Dr Gerard Rauwerda (Recore Systems)
• 12:00
DSP and FPGA: Competition, Synergy, and Future Integration in Space ASICs 30m
Speaker: Dr Roland Trautner (ESA/ESTEC)
• 12:30 12:55
Round Table Discussion - DSP and FPGA

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Convener: Dr Roland Trautner (ESA/ESTEC)
• 12:30
Open discussion on synergies of DSP and FPGA IP, related user requirements, and industrial views 25m
Speaker: Dr Roland Trautner (ESA/ESTEC)
• 12:55 13:00
ESA DSP Day 2016 - Wrap-up and Conclusions
Convener: Dr Roland Trautner (ESA/ESTEC)
• 13:00 14:00
Lunch 1h