Speaker
Mr
Bernard BANCELIN
(ATMEL NANTES S.A.S.)
Description
Mixed Analog / Digital System on Chip are increasing drastically in space equipment to reduce cost, power and dimensions and to improve performances.
The challenge for mixed SoC is to get a qualified product without heavy SEE or TID testing. As for a digital library, analogue cells and their combinations, High voltage LDMOS, regulators (to allow single supply) and latch-up protections must be “pre-qualified”.
The qualification of IOs and digital is done by using a Standard Evaluation Circuit covering at least half of the maximum of transistor of an ASIC.
For the analog part all blocks must be validated. In addition, in order to check the “integrability” of the building blocks towards the elaboration of a complex space-adequate System-on_Chip, a complex function will be realized embedding all individual analog cells and a digital block embedded as an analog cell.
During the realization of this complex function emphasis is given to the observability and testability of the individual building blocks. For each new analog cell the same process must be conducted. The study will continue by determining the observability of the analog nodes and specifically the eventual propagation of Single Event Transient. This study is conducted with support of ESA and CNES and with European industrial partners.
ATMEL ATMX150RHA offers a wide range of capabilities to enlarge the SoC integration: digital integration up to 20M gates, NVM, analogue, 3Gbit serial interface, N and P deep well, Deep Trench to isolate blocks, handle Wafer contact, 1.8V digital core, 3V, 5V, 15V and high voltage up to 60V. Mixing power, high voltage and high speed on a single chip needs adequate packaging technology, large die and small die must be handled by different packaging solutions: double pad ring, flipchip, Au bonding, Al bonding.
ATMEL can base the qualification for space requirements on standard process used in high volume. It ensures longer process lifetime and stability, as well as lower access cost. Same advantages applies to probe, assembly and final test. A mixed Standard Evaluation Circuit is under definition in order to check the “integrability” and “space testability and observability” of the building blocks.
The flow and the rules for integration of analogue cells coming from multiple suppliers will be clearly defined and qualified.
Key words: mixed Soc, embedded NVM, high voltage LDMOS, mixed MPU, mixed MCU
Primary author
Mr
Bernard BANCELIN
(ATMEL NANTES S.A.S.)
