Speaker
Mr
Laurent Berti
(IMEC)
Description
In the context of the microcontroller project developed for Cobham-Gaisler, IMEC extended and improved its IPs portfolio of the DARE180U library:
* 11 bits SAR ADC
* Extended input range PLL
* Cristal oscillator
* Power On Reset
* 1.8V and 3.3V voltage monitor
* GPIO with local Power On Control
* High density SRAM
All these IPs are hardened as the rest of the DARE180U library against radiation and heavy ions. If not explicitly defined the hardening level is respectively 300 krad for TID and 60 MeV*cm2/mg for the LET.
**High density SRAM (DARE180U_HDRAM)**
This dual port SRAM uses only 1.8V straight transistors in order to reduce the memory cell area. All the other hardening techniques against leakage between N-type regions and against latch up are kept. This IP has a fixed size of 4096 words of 39 bits for a total area of 2032x2180 µm2.
**GPIO with local POC (DARE180U_GPIO)**
This general-purpose IO can be used as:
* Digital input (Schmitt trigger) with programmable pull up/down
* Digital output (4mA)
* Analog input (serial impedance of 50 Ohms)
* Analog output
This IO when configured in digital input/output mode is completely SET free and uses only ELT layout for the NMOS transistor to make it insensitive to radiation effect.
Its local Power On Control forces the IO output in high impedance mode as long as the core voltage is not turned-on. Practically this high impedance mode will be maintained after the ramp-up of the core voltage thanks to the Power On reset.
**Voltage monitor (DARE180U_VMON)**
This block monitors the value of the 3.3V and 1.8V supplies. The detection threshold can be adjusted thanks to 3 bits of configuration from 1.6V till 1.77V for the 1.8V version and from 2.9V to 3.24V for the 3.3V version. To avoid false triggering due to noise on the supply a filter drops out any glitches shorter than ~20µs.
**Power On Reset (DARE180U_POR)**
The power on reset block generates a long reset pulse during the power-up of the core supply. The reset pulse duration can be adjusted thanks to an external capacitor. The typical pulse duration value is 235µs without external capacitor and 150ms with an external capacitor of 220nF. Considering the importance of the reset signal, this IP is obviously also SET free till 60 MeV*cm2/mg.
**Cristal oscillator (DARE180U_XO)**
The crystal oscillator delivers a stable CMOS level clock signal, using a crystal as input. The XO can be used with a 5 MHz and 25 MHz crystal. The oscillator is hardened against radiation but also against SET: no false edges on the clock can appear and the maximum period error is of 1.1ns and 3.8ns when respectively running at 25 MHz and 5 MHz (60MeV*cm2/mg).
**Extended input range PLL (DARE180U_PLL_EXT)**
The Phase-Lock-Loop (PLL) IP generates an output clock frequency that is an integer multiple of the input signal frequency. The ratio between the input frequency and the VCO frequency can be programmed to 8, 16, 20, 32, 40 and 80. The VCO of this PLL has been optimized from hardening point of view when running at 400MHz. At that VCO oscillation frequency, the maximum PLL output phase error due to a SET (60MeV*cm2/mg) is of 160ps and no false edge can appear. In absence of SET the PLL output signal has a jitter of 600fs in typical conditions.
**11 bits SAR ADC (DARE180U_ADC)**
This IP is composed of mainly 2 blocks:
* An analog mux 4:1 combined with an auto zeroed-amplifier (0dB, 6dB and 12dB).
* A differential and single ended SAR ADC (11b, 300kS/s) with internal voltage reference.
All the digital is hardened against SET and SEU:
* Use exclusively rad-hard FF (HIT).
* The data out bits are SET free thanks to a Muller-C filter.
* Clock path hardened by drive strength.
* The signals driving the switches connecting the capacitor to the voltage reference are not SET free till 60 MeV*cm2/mg, but any SET on these signals will be filtered thanks to the limited analog bandwidth.
The capacitor matrix and their switches are insensitive to “SEU” (i.e. permanent capacitor charge error) except on the capacitor bank side connected to the comparator. Indeed, if during the conversion a charge is injected when the switches connecting the capacitors to the voltage references are on, this charge is stored in capacitor bank. The sensitive junction area of these switches is in differential mode of 2*120µm2, this represent only few event on the total duration of a space mission.
The comparator itself is not completely immune to SET but its cross section is quite low and represents only few events (threshold 1 LSB) during one complete space mission.
Summary
In the context of the microcontroller project developed for Cobham-Gaisler, IMEC extended and improved its IPs portfolio of the DARE180U library:
- 11 bits SAR ADC
- Extended input range PLL
- Cristal oscillator
- Power On Reset
- 1.8V and 3.3V voltage monitor
- GPIO with local Power On Control
- High density SRAM
Primary author
Mr
Laurent Berti
(IMEC)
Co-authors
Mr
Bert Blockx
(IMEC)
Mr
Geert Thys
(IMEC)
Mr
Giancarlo Franciscatto
(IMEC)
Mr
Guillaume Pollissard
(IMEC)
Mr
Jey Ngole
(IMEC)
Mr
Koenraad Vanhoutte
(IMEC)
Mr
Staf Verhaegen
(IMEC)
Mr
Stephane Zagrocki
(IMEC)
Mr
Steven Redant
(IMEC)
Mr
Wim Sijbers
(IMEC)
Peer reviewing
Paper
Paper files:
