Speaker
Mr
Michael Kakoulin
(IMEC)
Description
In the last decades the evolution of the technologies for space ASIC and chip production is bringing a high level of miniaturization, giving benefits in terms of less power consumption, less mass, less volume, reduced number of components on the boards, better testability, higher performances and reliability. Newest space technologies (optical and RF communications) as well as miniature CubeSats and communication satellites are demanding more and more performance from electronic components. At the same time, satellites’ reliability and lifetime requirements are still requesting for TID and SEE radiation hardness. Space System Designers are always looking for the best integration, area, power, performance, mass, volume, radiation hardness and cost tradeoffs. Hence, there is always a demand to go for not only nodes with more capabilities, but also to more advanced nodes, for they bring new capabilities to the playing field. As the lead time to access new technologies for the development of ASICs for Space applications is several years, and the long-term availability is limited by the technology lifetime, it is important to give system designers for Space applications access to these technologies as early as possible.
DARE65T is a new radiation hardened (RH) high-performance system-on-a-chip (SoC) design platform including mixed-signal and analogue building blocks. It is built on the commercial TSMC 65nm LP 1.2V/2.5V CMOS technology. The DARE65T incorporates a set of standard and IO cell libraries, LVDS and SSTL cell libraries, memory and analogue IPs. The DARE65T development is based on common radiation design rules, which are implemented in an analog design kit (ADK). This approach facilitates also full custom radiation aware analogue design. DARE65T meats the main performance requirements of Space equipment designers.
The paper is focusing first on the irradiation test results of 65nm CMOS structures. This is significant step to define the design platform basis concerning radiation effects (TID, SEL, SEU, SET) mitigation methods. Second paper section is general overview of ADK development. The ADK incorporates and provides automatic checks of all chosen design rules, designers must follow in order to create RH ASICs. Another important point when doing radiation hardening by design for mixed-signal and analog blocks is simulation of SET events. ADK also provides the environment for such simulations.
Standard cell and IO cell library is a next step of platform development and thus next paper section. The paper gives an overview of standard cell layout template, used design methods against SEL and SEU. The DARE65T_CORE library has several types of cells allowing for designers to choose the right optimum between SEU/SET hardness level and area.
As it was mentioned in the introduction the Space designs are demanding more and more performance. The ASIC performance means not just a clock frequency, but also high-speed interfaces. Among classical requirements for LVDS IO cells in order to build SpaceWire interface links, there are new requests for DDR interface and high-performance link, for example RapidIO or PCIe or JESD204. DARE65T platform supports such needs providing set of LVDS and SSTL IO cells. The relevant section of the paper gives detailed overview of such platform capability.
Last paper section represents the analogue IP and memory IP which are the significant building blocks of future ASICs intended for space application. It also describes the main functional features and electrical parameters.
DARE65 libraries are reliable design platform for competitive high-performance radiation hardened ASICs.
Primary author
Mr
Michael Kakoulin
(IMEC)
Co-authors
Mr
Bilal Chehab
(Imec)
Mr
Geert Thys
(Imec)
Mr
Giancarlo Franciscatto
(Imec)
Mr
Guillaume Pollissard
(Imec)
Mr
Laurent Berti
(Imec)
Mr
Staf Verhaegen
(imec)
Mr
Steven Redant
(imec)
