Speaker
Mr
eric leduc
(1967)
Description
Leader of Microcontroller, Mixed-Signal and ASICs solutions since 30 years, Microchip has developed a large ASICs offer based on 0.8µm to 150nm technologies.
The ATMX150RHA ASICs offer is based on 150nm SOI proprietary technology with a Rad-Hard process. This technology is qualified through ESCC and DLA standards for 22Mgates 1.8V & 3.3V digital circuits.
Mixed-signal challenge has been addressed through a fully electrical and radiation characterization of elementary devices, using different test chips: Standard Evaluation Circuit (SEC) & Analog Test Vehicle dedicated to:
- Digital blocks: hardened standard-cells, hardened Flip-Flops & compiled memories
- Analog IPs: Voltage regulator & reference, clock synthesizer & signal conditioning.
A large choice of devices are available as MOS 1.8V, 3.3V, 5V, 15V and LDMOS 25V&45V, developed and simulated in the range of -55°C to 145°C junction temperature.
This paper presents the current radiation overview of the ATMX150RHA devices contained in the PDK. Are covered the following items: Single Event Latch-up (SEL), Total Ionizing Dose (TID), Single Event Gate Rupture (SEGR) & Single Event Burn-out (SEB) for HV devices. A focus is done on Single Event Transient (SET) & Single Event Upset (SEU).
SEL
The ATMX150RHA technology, using a Partially Depleted SOI is naturally SEL immune by implementation of Deep-trench capability. Nevertheless, Microchip has developed a high density processed solution for digital and compiled memories to keep SEL immunity without use of Deep Trenches.
High radiation SEL capability has been demonstrated with a SEL LET threshold > 60 MeV.cm2/mg.
TID
The ATMX150RHA technology is RHA level R for low voltage devices. High radiation TID capability has been demonstrated with:
- TID threshold > 100 krad(Si) for 1.8V to 3.3V devices.
- TID threshold between 30 krad(Si) and 50 krad(Si) for other devices and some IPs.
Post rad TID spice models are available for LDMOS.
SEGR&SEB
Post Rad SOA are introduced for LDMOS devices after SEGR and SEB characterization.
SET/SEU
Single Error Rate are available for ATMX150RHA standard cells, memories and some IPs after characterization of SET/SEU effects.
The high Single Event Transient (SET) soft error rate of integrated technologies becomes a major concern. It is the reason why the SET pulse width measurements or calculations are necessary to determinate the SET circuit sensitivity and optimize the radiation hardening. Thus, the measuring and modeling of the widths of transient voltage pulses are critical for the prediction and mitigation of soft errors.
The RAdiation Prediction TOols on Rhbd (RAPTOR) is a platform able to model the SET pulse width and assess the sensitivity of circuits to SET/SEU by considering the topology of the layout, the power supply, the logical states, the logic masking, the narrowing and/or broadening of the SET pulse widths.
This platform is a suite of tools including the software MUSCA developed and supported by the ONERA, and a list of MICROCHIP® proprietary tools developed in the framework of this project. The challenge was to integrate MUSCA® into a MICROCHIP® design flow and propose a user-friendly platform usable by all the designers.
The tool has been successfully validated on standard cells (combinatory cells and sequential), and complex circuits such as clock trees. The platform is now integrated in the design flow, and each new digital IP or standard Cells is assessed to SET/SEU by using RAPTOR.
The adding value of RAPTOR is its ability to assess easily, and in a short time the radiation sensitivity of a circuit, IP or standard cell. The effort deployed on the user-friendly interface is a plus. Also, RAPTOR is a key tool to improve the customer support on the radiation hardening.
Primary author
Mr
eric leduc
(1967)
Co-authors
Mr
David Truyen
(Microchip Technology)
Ms
Severine Furic
(Microchip Technology)