Apr 9 – 11, 2018
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
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UVVM - Universal VHDL Verification Methodology. Setting a standard for VHDL testbenches

Apr 9, 2018, 11:30 AM
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands


Mr Espen Tallaksen (Bitvis)


For an FPGA design we all know that the architecture – all the way from the top to the micro architecture – is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench. Most FPGA designs are split into stand-alone modules – for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities (components), and they are normally accessed from a CPU via a more or less standardized register interface, which acts as an abstraction layer. This abstraction allows a safe and very efficient control of the complete FPGA. It is clear that this approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse. UVVM provides a very simple and powerful architecture for this – to allow designers to build their own test harness much faster than ever before – using a mix of their own and open source verification components. Constrained random and Functional coverage may be used seamlessly with UVVM, and a current ESA project will make it simpler to control these features and combine with scoreboards, error injection, monitors and more. UVVM is only two years old, but has received great feedback from both users and large international players, and is already being used world-wide. The next major step for UVVM is an on-going project with ESA to make this verification methodology even better. This presentation will show you 1) how simple a UVVM testbench is to understand, build and control 2) how UVVM is standardising the VHDL testbench architecture 3) how the new ESA extensions will complete the VHDL testbench environment


FPGA verification is extremely important for good quality. The testbench architecture is the basis for verification quality, but also for verification efficiency, and most testbenches today could easily be developed 20 to 50% faster and at the same time improving the total product quality.
Many testbenches are terrible with respect to both quality, efficiency and reuse, and two main reasons for this are lack of competence and lack of a defined structure.
This is where UVVM can really help, as UVVM is a very structured approach to top level test harness, verification modules and high level (transaction level) commands.
UVVM is a game changer.

Primary author

Mr Espen Tallaksen (Bitvis)

Presentation materials