Speaker
Dr
Raoul Velazco
(Laboratoire TIMA)
Description
This presentation describes a method devoted to SEU error-rate prediction for processor-based architectures. The proposed method combines results issued from fault-injection, performed at circuit by means of CEU (Code Emulated Upsets), to those issued from radiation ground tests. It allows predicting error rates without requiring radiation ground-tests for future applications. The approach was successfully applied to processors and FPGAs and is illustrated by three representative case-studies.
Primary author
Dr
Raoul Velazco
(Laboratoire TIMA)
