12-16 November 2018
ESA/ESTEC
Europe/Amsterdam timezone

Error-rate Prediction for Programmable Circuits: Methodology, Tools and Studied Cases

13 Nov 2018, 17:00
1h
Newton 1-2 (ESA/ESTEC)

Newton 1-2

ESA/ESTEC

Keplerlaan 1, 2200 AG Noordwijk The Netherlands
Tests and simulations Tests and simulations

Speaker

Dr Raoul Velazco (Laboratoire TIMA)

Description

This presentation describes a method devoted to SEU error-rate prediction for processor-based architectures. The proposed method combines results issued from fault-injection, performed at circuit by means of CEU (Code Emulated Upsets), to those issued from radiation ground tests. It allows predicting error rates without requiring radiation ground-tests for future applications. The approach was successfully applied to processors and FPGAs and is illustrated by three representative case-studies.

Primary author

Dr Raoul Velazco (Laboratoire TIMA)

Presentation Materials