17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

Flexible FPGA Architecture for Compact High-Performance PDHU and OBC Mass Memory

19 Mar 2020, 15:15
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Industrial Experiences Industrial Experiences

Speaker

Dr Gang Zhou (DSI Aerospace Technologie GmbH )

Description

The dilemma of on-board payload data-processing units has not changed for decades: the resolution of remote sensing units is continually increasing so that the data rate is ever-increasing while the downlink bandwidth remains limited. The demand on compact and high-performance data handling and data storage modules is growing rapidly. The design must be scalable and very flexible to meet different capacity and data rate requirements. At the same time, the flexibility should not harm the maturity of the design since high-quality must be guaranteed under tight schedule.

We will present a flexible FPGA architecture, which implements the most timing-critical data acquisition, buffering, storage and downlink functions in a compact and high-performance PDHU which was presented on DASIA 2019 [ Paper Title: A Compact High-Performance Payload Data Handling Unit for Earth Observation and Science Satellites]. The main PDHU features are:
• Scalable Flash controller, up to 4 partitions can be supported. The mass memory capacity is scalable.
• Flexible logical to physical address mapping. The parallel accessed flash devices may have different flash block addresses so that flexible wear levelling algorithm can be supported in software.
• Flexible flash access interleaving scheme to maximize the flash interface performance.
• Double symbol error correction (Reed-Solomon) for flash mass memory.
• Flexible packet management: e.g., packet store based file management; logical address based mapping; application identifier based mapping; customized mapping.
• All memories (external and internal) are EDAC protected (Hamming / Reed-Solomon).
• Variable payload interfaces, e.g. WizardLink, SpaceWire, Channel links, etc.
• Variable downlink interfaces, e.g. WizardLink, LVDS parallel interface, etc.
• External SRAM as context memory to amend internal BRAM limitation (especially for RTAX FPGA).
• Variable TM/TC interfaces, e.g., CAN-Bus, MIL-Bus, SpaceWire, UART, HPC (high power command), RSA (relay status acquisition), etc.
• Implementation on RTAX / ProASIC3E / RTG4 FPGAs.
• On RTAX FPGAs, 2.2Gbps data acquisition + 640Mbps data downlink reached in an industry project.
• On RTG4 FPGAs, aggregate 6Gbps for simultaneous acquisition and downlink.
• Optional online/offline data compression/encryption.

As a result, the architecture has been implemented in the JUICE mission (on-board computer mass memory board), Biomass PDHU, FLEX PDHU, KACST Satellite Computer Board with mass memory, Mass Memory Module for KARI Kompsat-7, S4Pro (H2020 demo project). The same architecture is further adopted in several on-going PDHU proposals as well. The architecture also allows the integration of OBC functionalities so that it serves as a potential OBC-MM as well. Detailed configurations (e.g., interfaces, capacities, data rates, etc) will be presented in workshop.

Primary authors

Dr Gang Zhou (DSI Aerospace Technologie GmbH ) Mr Andre Schaefer (DSI Aerospace Technologie GmbH ) Mr Steffen Thiermann (DSI Aerospace Technologie GmbH) Dr Martin Herrmann (DSI Aerospace Technologie GmbH ) Mr Ole Bischoff (DSI Aerospace Technologie GmbH) Prof. Harald Michalik (IDA TU Braunschweig) Dr Christian Dierker (DSI Aerospace Technologie GmbH) Dr Ulf Kulau (DSI Aerospace Technologie GmbH ) Mr Elias Hashem (DSI Aerospace Technologie GmbH )

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