Forward Error Correction (FEC) is a mission critical onboard data processing task, providing continuous and reliable data transfers to ground stations even at low Signal-to-Noise Ratio (SNR) regimes.
The Consultative Committee for Space Data Systems (CCSDS) has standardized a number of protograph-based Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes for deep-space (AR4JA) and near-earth (C2) channel coding, as alternatives to concatenated convolutional and Reed-Solomon codes. The recommended LDPC codes (AR4JA and C2) outperform their predecessors in every aspect, including power, spectral efficiency and bit error rate (BER) performance, especially in the error-floor region.
Onboard implementation of CCSDS LDPC FEC imposes strict requirements on Size, Weight, Power and Cost (SWaP-C). Moreover, very high data-rate performance is required to enable a seamless integration within a high-speed onboard data processing chain to support Gigabit rate payloads (e.g. synthetic aperture radar and hyper-spectral optical instruments) and leveraging next-generation very high-speed serial link and network technology (i.e. SpaceFibre).
A novel architecture has been developed for high data-rate efficient hardware implementation of the CCSDS LDPC FEC which leverages the inherent parallelism of the CCSDS code structure, by concurrently processing multiple bits, according to an optimized scheduling.
We demonstrate the implementation of CCSDS LDPC FEC for deep-space and near-earth communications in the form of onboard hardware accelerator IP Cores targeting different space-grade FPGA technologies. The FPGA technology agnostic CCSDS LDPC FEC encoders achieve state-of-the-art throughput performance, ranging in the area of multiple Gbps. At the same time, resource utilization is kept at a minimum. A detailed throughput performance assessment will be presented along with implementation comparison results for different space-grade FPGA technologies.