Aerospace and Avionics ICs reliability depends on their ability to withstand the effects of radiation that naturally occurs in space and the Earth’s atmosphere. Radiation can cause Single Event Upsets (SEUs) and other types of faulty behavior in the design elements, which is transient by nature (recovery is possible). ICs are also susceptible to silicon aging effect, which may result in permanent faults (non-recoverable).
Measurements of effects of faults and their coverage through fault simulation is an area in Functional Safety that has been fast evolving in recent years, and could be leveraged for the aerospace chip design industry as well, both for soft IPs and for full FPGA designs. Methodologies and tools to measure safeness of potential faults, and the fault coverage of added safety mechanisms (such as TMR, ECC, DCLS etc.) have been implemented by various vendors. The challenge, though, is to enable an efficient and cost effective fault campaign to measure safeness and fault coverage on a modern, large scale design.
The presentation will demonstrate best-in-class tools and methodologies, using unified fault classification language, to manage the complex task of a fault campaign.