Vison-based navigation systems make use of image processing algorithms which are very computationally demanding in terms of memory and processing load.
In space domain the development of robust and efficient vision-based navigation systems is a key point to implementing autonomous navigation systems used in space exploration, active debris removal and rover vehicles. However, the tight constraints in space domain in comparison with other sectors above-mentioned makes that developments a great engineering challenge. Space devices have to fit hard constraints in terms of radiation hardened, environmental conditions, power consumption and FDIR (Fault detection, isolation and recovery). All of this makes space devices presenting lower performances than COTS (Commercial Off-The-Shelf) devices. Taking into account that an OBC (On board computer) should perform many other task with a tight timing constraints, it is really difficult to perform complex image processing at the same time. For that reason, accelerator devices are used in order to offload the OBC of the most computationally demanding parts as the image processing or low-level sensors management and pre-processing of data. In GMV we are designing HW accelerators based on Rad-hard SRAM-based FPGAs (Field Programmable Gate Array).
The main problematic in this type of architectures is how microprocessor and accelerator devices are going to communicate each other (physical interfaces, network and transfer protocols). It is possible to define different architectures depend on the services and capabilities implemented in the accelerator devices, from use of simple wire connections without communication protocols (row data transmission) to use of space qualified interfaces and communication protocols. In this way, GMV has developed a scalable architecture widely used on IPBs (image processing boards) in different ESA projects as CAMPHORVNAV (Vision-based Navigation Camera Engineering Model for Phobos Sample Return), MSR (Mars Sample Return), HERA or NXARTAN (Localization and Mapping adaptation for BRAVE devices).
This architecture provides the capabilities to have a network of devices running in parallel an independently different accelerator algorithm, having at all the time control of each accelerator and device from OBC and adding HW reconfiguration capabilities. For this purpose, SpaceWire is used to communicate and control the device network while PUS (Packet Utilization standard) over CCSDS Space packet protocol is used to Identify and manage the different accelerators and devices itself. This architecture has been already validated including 2 FPGA with separated functionalities, one of them acting as master managing interfaces, modes and self-tests while the other FPGA is fully devoted to the computer-vision accelerators. GMV is currently designing second version of these devices using only European Rad-Hard SRAM FPGA, NG-MEDIUM combined with NG-LARGE.