17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

Designing a low-latency Fail-operational motor controller for space on industrial-grade FPGAs

19 Mar 2020, 16:05
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Industrial Experiences Industrial Experiences


Aloïs Wolff (Watt&Well)


Permanent Magnet Synchronous Motor (PMSM) control is a field where real-time processing capabilities play a substantial role in the system’s performance. The usual tradeoff for the processing elements amounts to choosing between a DSP or an FPGA, with the latter seen as more complex to develop and maintain.

This tradeoff usually does not hold out against the specific constraints in the space industry: radiative environments causing SEEs (Single Event Effects), fault tolerance and reliability constraints. One favored answer was to rely on a thoroughly screened space-grade FPGA to bear the brunt of the reliability goals. However, the strong push to reduce recurring costs provides an incentive to explore architecture-based fault-tolerance solutions, where cheaper components verify each other dynamically.

In this talk we present a distributed motor control architecture based on GUARDS (“A Generic Upgradable Architecture for Real-Time Dependable Systems”) allowing:

  • A 40kHz motor control loop robust to any single (permanent or intermittent) fault
  • Undisturbed operation in a SEE environment
  • Distributed FDIR and telemetry

We will then explain why using an industrial-grade FPGA is a particularly good fit for this type of architecture, and how we make it work at Watt & Well: Rapid prototyping on reprogrammable FPGAs allows for quick algorithm de-risking; The inherent parallel architecture of FPGAs allows both flexibility in protocol design and make meeting the real-time deadlines easier; Finally, fine-grained verification capabilities make reaching a very high design assurance level a systematic process.

Primary author

Aloïs Wolff (Watt&Well)

Presentation Materials

There are no materials yet.