17-19 March 2020
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

FPGA implementation of Cloud Detection algorithm based on Convolutional Neural Network for Earth Observation applications On board

19 Mar 2020, 12:10
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Artificial Intelligence/Machine Learning Artificial Intelligence/Machine Learning

Speakers

Mr Giamarco Dinelli (University Of Pisa)Mr Gionata Benelli (IngeniArs)

Description

In the last years, Machine Learning has rose in popularity, and also the space community has started to consider AI-based algorithms as a promising solution for tasks such as spacecraft navigation and on-board image elaboration. ESA project CloudScout, flying on mission PhiSat-1/FSSCAT on-board a 6U CubeSat, has the aim to show the feasibility of AI-based algorithms in orbit to perform computer vision tasks. In particular, CloudScout is able to discard Earth surface images covered by clouds in order to maximize the quality of downloaded data, using a Convolutional Neural Network (CNN) algorithm realized by University of Pisa. On PhiSat-1, the algorithm will run on a COTS hardware accelerator, the Myriad-2 by Intel Movidius. Since the Myriad-2 requires an Operative System (OS) and Eye-of-Things board mounting the chip offers a limited set of high speed communication interfaces (USB and CIF), we decided to implement the cloud-detection algorithm on an Xilinx XCKU60 FPGA. This solution does not require an OS and can support any high-speed protocol. The proposed hardware architecture is able to perform an inference with the same performance of the Myriad-2, 300ms, requiring 25% of the LUT, 2% of the FF and 53% of RAM blocks for storing weights and data to be processed.
Since the realized hardware accelerator does not fit on space-grade FPGAs (i.e. Microsemi RTG4 and NanoXplore Brave Large) we decided to work on the software model to reduce its complexity, and on the hardware architecture in order to produce a simpler and reusable design.
The algorithm was slightly modified to reduce the number of computations required by removing max-pooling and performing sub-sampling during convolutions by increasing the stride parameter. The hardware design focused on the optimization of the usage of memory resources available on-board the FPGA, which represented the bottleneck of the previous design, since CNNs require a large amount of data to perform simple computation.
The result of the preliminary analysis shows that thanks to both software and hardware optimization, it would be feasible to implement the cloud-detection algorithm on target devices taking into account both hardware resources and inference time constraints.

Primary authors

Mr Giamarco Dinelli (University Of Pisa) Mr Tommaso Pacini (University of Pisa) Mr Emilio Rapuano (University of Pisa) Dr Gabriele Meoni (University of Pisa) Prof. Luca Fanucci (University of Pisa) Mr Gianluca Giuffrida (University of Pisa) Mr Gionata Benelli (IngeniArs) Dr Daniele Davalle (IngeniArs S.r.l.)

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