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Description
This paper presents the test vehicle (TV) of the rad-hard library developed at IMEC, referenced with the acronym DARE22G, that reflects the “Design Against Radiation Effects in 22nm”. Thanks to this test vehicle, the functional validation, the electrical performance, and the radiation hardening and sensitivity (SEE and TID effects) of the DARE22G library and a commercial DPRAM will be performed.
The TV includes; 1) digital core cells, mainly 228 combinatorial logic cells, 48 clock gating, 5 radiation-hard (DICE) and 12 standard sequential flipflops. 2) IO cells, including bidirectional digital IOs, and LVDS. 3) a TID sensor with an adaptive back-bias generator, 4) voltage and current references, 5) a 3GHz ultra-low jitter Phase-Locked Loop. 6) 1 GHz ring oscillators. 7) a commercial DPRAM. 8) a radiation-hard SPI (Serial Peripheral Interface) controller and control/monitor registers have been integrated to this TV, in order to control the testing of all the previous blocks.
Multiple instances of the digital core cells and DPRAMs are necessary to achieve enough sensitive area for the SEE testing. This has been respected for all the victims under the test, except for the radiation-hard flipflops. In fact, to fit inside the available area for this TV (15mm2), the sensitive area of these flipflops has been divided by two, and only 5 relevant flavors of the 12 available have been selected. However, the radiation exposition time for these DICE flip-flops will be doubled with respect to the statistical relevance.
Many structures have been designed to allow the SEE testing of the different blocks. For instance, the combinatorial logic cells have been split in many parallel short chains with maximum 24 cells, to limit the pulse broadening effect. A specific block called Combiner, is designed to merge these parallel chains into one node (making data handling more manageable). Beside the SET detection of the combinatorial logic cells, the duration of these events will also be estimated.
The 1Ghz ring oscillators are intended to evaluate the delay variation of the logic gates versus TID. But also, to calibrate the delays used for the estimation of the SET duration.
Beside the SET detection for the clock gating cells, the propagation of such events between victims can also be detected. The SEU hardening of the commercial DPRAMs, and the sequential flip-flops will be tested by a comparison of the contents of these cells before and after irradiation.
Fast comparators have been designed to allow the SET detection of the voltage references. IO receiver cells are equipped with SET-detecting latches; IO transmitter cells are connected in analog loopback mode to two receiver cells with SET-detecting latches, to distinguish between RX and TX SET effects.
Using the TID sensor, the adaptive back-bias generator automatically compensates for any TID effects by trimming the back-bias voltage to a level where the digital circuitry performance can be maintained.
The 3GHz PLL has been designed to guarantee a jitter lower than 300fs. To be able to measure such low jitter with a standard 256 CPGA package, a dedicate buffer with a specific IOs ring has been designed.
Acknowledgement:
The authors would like to thank the European Commission. This project (EFESOS) has been funded from the European Union’s Horizon 2020 research and innovation programme.
