The aim of this communication is to present the hardening approach that has been followed towards the realisation of a hardened DDR3 PHY when targeted on the C65SPACE platform of ST Microelectronics. The implementation concerns the flip-chip version of the IP. The key points that will be presented are: i) the key requirements the PHY IP should meet, ii) the PHY architecture, iii) the RTL to...
In this article, we report the design of new analog and digital IP in 22nm FDSOI and against radiation effects (DARE). The purpose is to enable a magnetic non-volatile random-access memory (MRAM) for space. A test vehicle has been taped out. It contains a range of analog IP for powering and clocking the test chip and to provide safe power up and down sequences. These blocks are integrated...
