Speaker
Description
“Over 80% of FPGA released into the field have a nontrivial error” – Wilson Group Survey
All RTL developers are familiar with coding standards which outline the rules which the RTL should be developed in accordance with. Enforcing these rules is normally the performed by peer review, which makes the enforcement variable.
A better approach to enforcing code quality is use of a static analysis tool which has a defined ruleset enabled. Static analysis of code enables a much wider, variety of analysis to be performed on the RTL which increases the quality of code which enters simulation and synthesis.
Static RTL analysis, however, is not limited to just the enforcement of RTL coding rules. Static RTL can be used by the engineering team to enforce
1. RTL coding rules – Clocking, Reset, Register Sizing, Unused Code.
2. FSM analysis – Deadlock, Terminal States, Unused State addressing.
3. Clock Domain Analysis – Detection of Clock Domains and creation of Constraints
4. Clock Domain Crossing – Analysis of the RTL for clock domain crossing issues
5. Path Analysis – Longest path between registers
This analysis enables better quality of code for simulation as for example FSM terminal states can be quickly identified in static analysis while in simulation it may take many hours for the design to progress to that branch of the FSM.
Over the last three years Adiuvo has partnered with ESA to use the Blue Pearl Visual Verification Suite to analyse the current ESA FPGA IP Library, against a defined set of RTL coding rules.
This session will start by explaining the agreed ruleset how it was defined, which standards were considered and why each of the rule final rules is important.
The session will then progress to identify common issues found in the ESA IP Library, despite being developed by several different institutions common issues are found.
To conclude the session, we will present the development flow developed to correct issues identified within the RTL without impacting the performance.
Static analysis of RTL code can help developers, identify problems which might be missed in simulation as the “right” question is not asked. As demonstrated in this project static analysis enables the identification of issues earlier in the development cycle which are easier to correct. Static analysis also creates evidence of peer reviews and analysis which can further support stage reviews such as PDR and CDR.
