Speaker
Description
Verification is critical for an acceptable FPGA quality, but unfortunately, achieving a good FPGA quality is often very time-consuming and difficult. However, with a good testbench architecture, the workload could be reduced significantly and at the same time really improve the quality.
UVVM provides the best VHDL testbench architecture possible and also allows a unique reuse structure. Entry-level UVVM is dead simple even for beginners, and for more advanced verification, the standardised Verification Components, the high-level SW-like commands and all the other features will allow even really complex verification scenarios to be handled in a structured and understandable way. UVVM is open source and provides a great testbench kick start with open source BFMs and verification components for UART, SPI, AXI, AXI-lite, AXI stream, Avalon MM, Avalon stream, I2c, GPIO, SBI, GMII, RGMII, Ethernet, Wishbone, Clock generator, and Error injector. Other equally important functionalities in UVVM are Advanced Randomisation, Functional Coverage, Watchdogs, and Specification Coverage. The latter allows very efficient requirement tracking and provides a Requirement Traceability Matrix - typically mandatory for space applications, functional safety, etc.
Major parts of the UVVM extensions over the last 5 years have been made in tight cooperation with ESA - during two UVVM-dedicated ESA projects. This has assured very good support for mission-critical FPGA development, but also for safer and faster FPGA development in general.
This presentation will give you a fast introduction to UVVM and show both simple and advanced features, and explain how they will help you make a better testbench - and develop this much faster.
