14–16 Mar 2023
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Presentations available

SoC-based architecture for high-security Satellite Quantum Communication (University of Padova)

15 Mar 2023, 18:05
25m
Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Erasmus High Bay

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
FPGAs: High Performance FPGAs: High Performance

Speaker

Dr Andrea Stanco (Department of Information Engineering, University of Padova)

Description

We present a System-on-a-Chip (SoC) architecture, based on Field Programmable Gate Array (FPGA), suitable for satellite quantum communication which exploits a COTS board, the ZedBoard by AvNet. Beside granting a very high flexibility thanks to its Zynq-7000 SoC, including both an FPGA and a CPU, this architecture allows to implement a “1-random-1-qubit” encoding where a unique random number, generated with no expansion from a Quantum Random Number Generator (QRNG), is used to encode a single qubit in a discrete variable Quantum Key Distribution (QKD) scheme exploiting the polarization degree-of-freedom of single photon.
The architecture has two main layers: one is implemented at CPU level and is responsible for the high-level functions (data transfer, parameters setting); the other is implemented on the FPGA to handle the high speed and deterministic functions (generation of the output signals driving the electro-optical setup). This offers a very high flexibility as the FPGA design is strictly reserved only to specific functions that require precise timing and high speed.
On the FPGA, 3 signals (5ns width) are generated with a repetition rate of 50 MHz (due to analog bandwidth limits). We also exploit both the CPUs to realize a continuous stream from an external source (QRNG/PC) through a 1-Gbps TCP connection which allows to have a continuous qubit transmission with no interruptions. Given a 4-bit encoding for each qubit (2 bits for polarization, 2 for intensity), we implement the architecture to sustain more than 200 Mbit/s. The data transfer is organized in two processes: from QRNG/PC to CPU0 where the data is stored into the on-board RAM memory; from CPU1 to FPGA where the data is moved from RAM to Block-RAM. The whole procedure is synchronized through interrupts (FPGA<->CPU1; CPU1<->CPU0; CPU0<->QRNG/PC). Over recent years, this system (or variation of it) was successfully used in several (satellite) QKD/QRNG experiments realized by the QuantumFuture research group. It was also implemented in the commercial QKD systems provided by ThinkQuantum, a spin-off company from University of Padova. Results were recently published in a peer-reviewed article (A. Stanco et al., DOI: 10.1109/TQE.2022.3143997).
The system was tested with a QRNG device, able to provide >200 Mbit/s, for 55 hours showing no interruptions and correctly delivering the data for the qubit transmission. Most of nowadays systems exploits a low-rate QRNG (~Mbit/s) and algorithm expansions to reach the required bitrate but with a major drawback in security as the transmitted qubit sequence is not fully random due to the expansion algorithms. Thus, our system offers a higher level of security for QKD thanks to the true randomness of the qubit sequence. According to the current state of the European and Italian satellite QKD missions, this represents a relevant result since such missions are considering payloads with both a QKD transmitter and a QRNG. Furthermore, as Cubesat technology is becoming more prominent and COTS components have started to find their place in space mission, a COTS-based system for a QKD-QRNG apparatus can be considered a valid baseline for satellite quantum communication.

Primary authors

Dr Andrea Stanco (Department of Information Engineering, University of Padova) Mr Francesco Bruno Leonardo Santagiustina (Department of Information Engineering, University of Padova) Dr Luca Calderaro (ThinkQuantum s.r.l.) Dr Marco Avesani (Department of Information Engineering, University of Padova) Mr Tommaso Bertapelle (Department of Information Engineering, University of Padova) Dr Daniele Dequal (Italian Space Agency (ASI)) Prof. Giuseppe Vallone (Department of Information Engineering, University of Padova) Prof. Paolo Villoresi (Department of Information Engineering, University of Padova)

Presentation materials