Speaker
Description
The talk will present the use of eFPGA for supporting application-specific, user-defined instructions in LEON2-FT. The work extends the SIMD-Within-a-Register (SWAR) concept, developed by daiteq for LEON2-FT and NOEL-V, with the aim to improve performance for applications such as GNSS or image processing where more data values can be stored next to each other in one processor register and processed by one assembly instruction in one clock cycle. In the presented work the SWAR concept is extended with eFPGA-specific aspects like interfacing and fabric reconfiguration with the overall goal to allow end users to define and use their own application-specific instructions in future ASIC versions of LEON2-FT and NOEL-V processors through describing the new instructions in HDL and generating a configuration bitstream that can be downloaded to the eFPGA during processor operation. We will show an implementation of custom instructions designed for GNSS processing and CCSDS121 image compression in the Menta eFPGA technology, and conclude with more general observations on efficient forms of custom instructions.
