14–16 Mar 2023
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Presentations available

Design on NG-ULTRA FPGAs using a HLS-to-Bitstream design flow (TAS)

15 Mar 2023, 10:45
25m
Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Erasmus High Bay

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Industrial Experiences Industrial Experiences

Speaker

Philippe MERCIER (Thales Alenia Space)

Description

We present an early evaluation of a flight-proven altimeter design implementation on NG-ULTRA FPGAs using a HLS-to-Bitstream design flow relying on Siemens-EDA Catapult (HLS) & Precision (synthesis) tools and NanoXmap design suite.
Our analysis focuses on three main aspects :
1) Provide feedbacks on the design flow developed by Siemens-EDA
2) Compare the performances of Precision with those of NanoXmap synthesis
3) Estimate the performances that can be achieved

Primary authors

Mr Mickael FIORENTINO Mr Gregory GRIMONET Philippe MERCIER (Thales Alenia Space)

Presentation materials