14–16 Mar 2023
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Presentations available

In-Orbit Artificial Intelligence and Machine Learning for Space Applications : Versal Space Reference Design : First Design-In Experiences (Spacechips)

16 Mar 2023, 09:30
25m
Erasmus High Bay (European Space Research and Technology Centre (ESTEC))

Erasmus High Bay

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Artificial Intelligence/Machine Learning Artificial Intelligence/Machine Learning

Speaker

Rajan Bedi (Spacechips Ltd)

Description

An increasing number of on-board processing applications require intelligent in-orbit processing to extract value-added insights rather than clog precious RF downlinks with bandwidths of data for post-processing on the ground. Some applications require autonomous, real-time decision making, e.g. a space-debris retrieval spacecraft outside of its ground-station coverage would not be able to receive a late command to initiate a collision-avoidance manoeuvre, or space-domain awareness from multiple sensors followed by object detection and classification may require an immediate friend or foe decision. High-definition SAR imagery is increasingly generating huge amounts of Earth-observation data and in-orbit AI inference and the implementation of neural networks allows for feature identification, scene segmentation and characterisation.

Space-grade FPGAs, ACAPs, MCUs with vector-processing engines and rad-tolerant AI accelerators optimised for linear algebra and neural networks, each offer certain advantages for intelligent on-board processing. Some applications require small, low-power, Edge-based solutions while others can accommodate 140 W semiconductors.

AMD/Xilinx’s Versal ACAP (Adaptive Compute Acceleration Platform) contains an array of AI engines comprising VLIW SIMD high-performance cores containing vector processors for both fixed and floating-point operations, a scalar processor, dedicated program and data memory, dedicated AXI channels and support for DMA and locks.

The AI tiles provide up to 6-way instruction parallelism, including two/three scalar operations, two vector reads and one write, and one fixed or floating-point vector operation every clock cycle. Data level parallelism is achieved via vector-level operations where multiple sets of data can be operated on a per-clock-cycle basis. Compared to the latest FPGAs and microprocessors, AI engines improve the performance of machine learning algorithms by 20X and 100X respectively, consuming only 50% of the power.

Spacechips is developing a space reference design baselining the XCVC1902-1MSEVSVA2197 ACAP which can be used for prototyping and de-risking future mission concepts, as well as a qualified version suitable for space flight.

This work compares the implementation of smart payloads baselining ultra-deep-submicron COTS parts, space-qualified FPGAs, ACAPs, MCUs with vector-processing engines and rad-tolerant AI accelerators. Each of these offers an intelligent processing solution depending on the space application, the required performance and operational mission constraints.

The work also describes the specification and capability of Spacechips’ Versal Space Reference Design, discusses our design-in experiences of the XCVC1902-1MSEVSVA2197 ACAP and the challenges of powering and thermally managing a large, 140 W semiconductor.

Primary author

Rajan Bedi (Spacechips Ltd)

Presentation materials