Speaker
Description
Future telecommunications satellites are envisioned to seamlessly integrate into the mobile communication networks of the next generation. First signs toward the integration are already visible today with the ongoing normative activities on non-terrestrial networks in the current 5G New Radio standard. A general goal in these next generation communication networks is to employ radio terminals that are more intelligent, automatically adapting their transmission to the current state of the spectral environment, in order to make better use of the scarce frequency resources. For realizing such highly adaptive radios, research mainly focuses on the use of algorithms in the Artificial Intelligence (AI) domain, in particular neural networks (NNs). As a result of the success that these methods showcase in the area of communications and beyond, there is a major desire in the satellite industry for deploying NNs and similar algorithms directly on-board of the satellites in space. The main challenges associated with that desire are the limited power budget and computing resources of satellites.
With the Versal Adaptive Compute Acceleration Platform (ACAP) in the XQR variant, AMD Xilinx now offers a chip in a space-grade package that is particularly targeted for machine learning applications in space, while promising more compute power than traditional FPGA-based systems-on-chip (SoCs). Combining an FPGA fabric with a new class of compute engines intended for parallel computing, including AI inference acceleration, this device opens up new opportunities in terms of on-board processing performance, but also comes with novel challenges in terms of system integration and application development for satellite manufacturers. An initial evaluation of the design flow and the capabilities of the platform is thus in the center of this presentation.
Starting, we will providing background information on contemporary deployment techniques of neuronal networks on FPGAs. Afterwards, we will focus on two modes of utilization of the Versal platform: First, the usage of Xilinx’s Deep Learning Processing Unit (DPU), which is a generic hardware accelerator built for deploying a variety of arbitrary deep-learning operations and applications, is elaborated. This is Xilinx’s straight-forward and out-of-the-box way of programming the Versal which performs computation on both programmable logic and AI-Engines. However, due to the lag of customizability, we introduce a custom co-processor design approach as an alternative to the DPU in a second step which focusses on utilizing the Versal’s AI-Engines, in this case especially for convolutional neural network operations, in a more controllable manner.
Lastly, the presentation is concluded by providing a brief dive into the three computing parallelism schemes on the AI-Engines.
