Speaker
Description
Nanoxplorer’s Field Programmable Gate Arrays (FPGA) and tools, which help a user integrate their Register Transfer Level (RTL) projects in Nanoxplorer (NX) FPGA portfolio, matured to the point, where a user with few clicks in Graphical User Interface (GUI) Impulse or python environment (NxPython3) build their RTL code for BRAVE FPGAs. The main goal of our practice was to evaluate the latest NX tools and test them with a complex open-source RISC V core (NEORV32 RISC-V processor) and integrate NEORV32 on NgMedium BRAVE FPGA. NEORV32 RISC-V processor is a customizable microcontroller (System on Chip – SoC) with a 32-bit processor which supports all RISC-V instructions, and its RTL is written in VHDL and Verilog Hardware Description Language (HDL). The NEORV32 processor core bases on RISC-V instruction architecture, and a user can attach to the core various peripheries such as UART, SPI, WatchDog timer, etc. The synthesis and integration steps were given in the Python script and then run with NxPython3. After the tool successfully generated bitstream for NgMedium FPGA, we uploaded it on the NgMedium development board. As with any other processor running on an FPGA, evaluation and benchmarking of the NEORV32 synthesized version was with software (SW), which runs a robot spider with four legs, and each leg has three joints. The spider movements are given in the cartesian and polar coordinate system and then described in C language. After compiling C code, SW required 32kB of Memory. To fit the spider application in the NEORV32 processor, the processor consumed around 12% of logical/sequential components and 22 Block RAM for instruction and data memory. Implemented NEORV32 core runs with a clock frequency of 37.5MHz, which is sufficient for the program to execute periodically every 20ms.
