NanoXplore's 5th BRAVE Days

European Space Research and Technology Centre (ESTEC)

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

The Fifth edition of NanoXplore User Day and Communication Event, in collaboration with ESA and CNES!

Here is what to expect:

• Updates and presentations on our latest products, partnerships and projects, as well as exclusive announcements about our future endeavors
• Conferences from users all around the globe, presenting how they used our highly performant technology in their defense and space projects
• A workshop on NanoXplore’s ecosystem, encompassing everything from our FPGAs and development suite to IPs providers and third-party tools
• Booths from us and our partners to experiment and discuss about everything NanoXplore related

And all of this completely free of charge!

See all the subjects covered and more at

Submission of abstracts is now open via our dedicated email address:
The deadline for submitting an abstract is July 13th.

Registration is required via this website, and an Indico account is required for it (company email address only, not personal one).

To create an Indico account go to the top right corner and choose “Log in”, then “create one here” and follow the given instructions.
After an account has been created you can register using this Indico event site.

5th BRAVE Days Registration Form
  • Tuesday, November 28
    • 9:00 AM
      Event Opening / Reception
    • 1
      Welcome and Introduction
      Speaker: Edouard Lepape
    • 2
      Company Update
      Speaker: Edouard Lepape
    • 3
      Impulse : Year One
      Speaker: Alp KILIC (Nanoxplore)
    • 11:15 AM
    • 4
      ESA Contribution
      Speaker: Mr David Merodio Codinachs (ESA)
    • 5
      BRAVE FPGA, GRLIB and GR765

      Frontgrade contribution

      Speaker: Mr Sandi Habinc (Cobham Gaisler AB)
    • 1:00 PM
      Lunch Break
    • 6
      Harnessing the Power of HDL Coder and Collaborative Integration with NanoXplore

      In the ever-evolving field of Field-Programmable Gate Array (FPGA) development, the synergy between advanced design tools and collaborative partnerships holds immense potential. This talk explores the transformative capabilities of HDL Coder, a powerful toolset for generating synthesizable HDL code from MATLAB and Simulink models, and its integration with NanoXplore, a leading provider of high-performance FPGA solutions.

      The talk highlights the collaborative efforts between HDL Coder and NanoXplore, showcasing their combined expertise in FPGA architecture and design optimization. A specific use-case in space missions, focusing on satellites, demonstrates how this integration enables efficient implementation of complex functionalities while overcoming space, power, and reliability challenges. Attendees will gain insights into successful satellite missions leveraging this collaboration, resulting in improved performance, reduced development time, and increased reliability in space environments.

      FPGA designers, algorithm developers, and system architects will learn how to leverage HDL Coder and NanoXplore for advanced space mission development.

      Speakers: Stephan van Beek (MathWorks), Ms Yanitsa Stoyanova (Airbus)
    • 7
      Speeding up DO-178C Safety Certification with Trace-based Code Coverage

      Collecting code coverage information is required for all the common software certification processes, including the one defined by DO-178C. This is usually a challenge because traditional code coverage measurement requires extensive code instrumentation which has all kinds of side effects like (additional) memory consumption, slowing down the execution, and much more. After discussing the overall added value of Lauterbach’s real-time-trace debug features for developers of any embedded application, this presentation explores the advantages of Trace-based Code Coverage for integration and system tests and demonstrates a practical example using an NG Ultra SoC by NanoXplore. We will observe and discuss the advantages of minimal or even zero code instrumentation used for Lauterbach’s new trace-based measurement method compared with the traditional source code instrumentation.

      Speaker: Mr Ladislav Řehák (Lauterbach)
    • 3:30 PM
    • 8
      Star Dundee Contribution

      SpaceFibre (ECSS-E-ST-50-11C) is an evolution of SpaceWire, being backwards compatible with SpaceWire at the packet level. SpaceFibre is a very high-performance, high-reliability and high-availability network technology specifically designed to meet the needs of modern space applications where very high throughput is required. It provides point-to-point and networked interconnections at Gigabit rates— more than 6.25 Gbit/s per lane for current FPGAs, with multi-lane allowing to reach up to 16 times the speed of a single lane —with Quality of Service (QoS) and Fault Detection, Isolation and Recovery (FDIR). SpaceFibre NORBY and OPS-SAT technology demonstrators have already flown SpaceFibre, with more missions in both Europe and the USA currently designing or planning to use SpaceFibre.

      STAR-Dundee has developed a complete family of SpaceWire and SpaceFibre IP cores fully compliant with these ECSS standards.

      A new generation of radiation-tolerant FPGAs is emerging to cope with the ever-growing processing power required by newer missions, the BRAVE FPGAs family is a good example of this new generation of FPGAs. SpaceFibre operation requires serial transceivers, which are already inbuilt in modern FPGAs. The SpaceFibre IPs have been adapted to take advantage of the specific transceivers and memory blocks offered by these new FPGAs.

      In this work we present the effort done to ensure that STAR-Dundee SpaceFibre IP cores work on the BRAVE FPGAs including simulation results from the verification with simulation models of the transceivers, post-synthesis resource utilisation and simulation of SpaceFibre IP and hardware tests done in the process.

      Speaker: Marti Farras Casas (STAR-Dundee)
    • 9
      Moon exploration with FUSIO RT- A scalable and configurable computer core
      Speaker: Pierre Berthet
    • 5:00 PM
    • 5:30 PM
      Cocktail Party
  • Wednesday, November 29
    • 8:30 AM
      Coffee and mingling
    • 10
      NEORV32 runs on NG-MEDIUM

      Nanoxplorer’s Field Programmable Gate Arrays (FPGA) and tools, which help a user integrate their Register Transfer Level (RTL) projects in Nanoxplorer (NX) FPGA portfolio, matured to the point, where a user with few clicks in Graphical User Interface (GUI) Impulse or python environment (NxPython3) build their RTL code for BRAVE FPGAs. The main goal of our practice was to evaluate the latest NX tools and test them with a complex open-source RISC V core (NEORV32 RISC-V processor) and integrate NEORV32 on NgMedium BRAVE FPGA. NEORV32 RISC-V processor is a customizable microcontroller (System on Chip – SoC) with a 32-bit processor which supports all RISC-V instructions, and its RTL is written in VHDL and Verilog Hardware Description Language (HDL). The NEORV32 processor core bases on RISC-V instruction architecture, and a user can attach to the core various peripheries such as UART, SPI, WatchDog timer, etc. The synthesis and integration steps were given in the Python script and then run with NxPython3. After the tool successfully generated bitstream for NgMedium FPGA, we uploaded it on the NgMedium development board. As with any other processor running on an FPGA, evaluation and benchmarking of the NEORV32 synthesized version was with software (SW), which runs a robot spider with four legs, and each leg has three joints. The spider movements are given in the cartesian and polar coordinate system and then described in C language. After compiling C code, SW required 32kB of Memory. To fit the spider application in the NEORV32 processor, the processor consumed around 12% of logical/sequential components and 22 Block RAM for instruction and data memory. Implemented NEORV32 core runs with a clock frequency of 37.5MHz, which is sufficient for the program to execute periodically every 20ms.

      Speaker: Klemen Bravhar
    • 11
      RISC-V for payload Control and Data Processing

      The FreNox RISC-V microcontroller IP has its heritage in numerous products for high-assurance and high-reliable security applications for data line encryption and network domain separation (i.e. NLD/EU/NATO-restricted). As a founding member of the RISC-V Foundation, Technolution has designed and implemented the FreNox RISC-V processor family. The FreNox RISC-V microcontroller IP has been integrated in numerous FPGA devices. We also ported the full AXI-4-based FreNox RISC-V system-on-chip into the radiation-hardened NanoXplore NG-Medium device, and have created a full interactive demonstration; through the SpW-interface we upload software in the RISC-V SoC, allowing the user to play the "Space Invaders" game on the NG-Medium board.

      We keep improving our RISC-V platform; for instance with processor-agnostic simple gdb remote interface, implemented and demonstrated in the FreNox RISC-V processor. We have designed and implemented a simple gdb remote interface for multiple platforms to make gdb over a serial link a practical proposition for embedded microcontroller use. The implementation comes with limited hardware overhead, and has been included in our full interactive "Space Invaders" demonstration.

      Under the Key Digital Technologies Joint Undertaking (KDT JU) TRISTAN project the RISC-V microcontroller design is being iterated for increased security and robustness for space application, such as implementing error and security checkers, lock-step operation, FDIR control and radiation testing.

      For SmallSat payload control and data processing, we foresee wide use of reconfigurable FPGA technology. So, we have started the development of a novel payload control and data processing unit that is able to serve the evolving SmallSat market and is a perfect-fit solution for compact instrument developers. The proposed modular payload control and data processing architecture provides a good separation of concerns between instrument developers and platform provider allowing short time-to-orbit of payloads and missions. It offers a combination of FPGA-based instrument control functions, interface flexibility and powerful data processing capabilities. Telemetry and telecommand handling and most instrument control functions will be covered by our RISC-V softcore microcontroller.

      Speaker: Dr Gerard Rauwerda (Technolution B.V.)
    • 12

      In recent years, research in the space community has shown a growing interest in AI, mostly driven by systems miniaturization and commercial competition. FPGA have proven to be competitive accelerators for these algorithms and works proposing methods for automating the design on these devices have acquired relevance. The common purpose is to enable a wide range of users without specific skills to accelerate AI models on FPGA with reduced development times.This presentation will focus on the characterization of FPG-AI, a novel technology-independent toolflow for automating AI deployment on FPGA, on NanoXplore devices. We will present preliminary information on the achieved performances in terms of computational power and resource consumption on a representative use case scenario.

      Speakers: Pietro Nannipieri, Pietro Nannipieri (University of Pisa)
    • 11:00 AM
    • 13
      Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs

      Radiation-Hardened-By-Design (RHBD) FPGAs have gained a lot of attention thanks to their excellent compromise between costs and performance. Being of very limited use due to a lack of performance a few years ago, these devices are now capable of implementing a wide range of applications requiring high computational capabilities.

      This work describes an implementation of a Very Long Instruction Word (VLIW) soft-core convolutional accelerator in the NanoXplore RHBD NG-Medium chip. Feasibility and timing performances have been analyzed in order to discover whether and how multi-core solutions can affect parallel acceleration. Placement also showed to heavily affect the delays, up to 70% more, based on the proximity to the output buffers.

      Speaker: Luca Sterpone (Politecnico di Torino)
    • 14
      Exploring the Latest High-Level Synthesis Results with Bambu: Insights from the HERMES Project's Use Cases

      Europe is working on improving competitiveness in the space services sector by developing radiation-resistant, high-performance microprocessors and simplifying the deployment of complex applications. The HERMES project aims to achieve a technology readiness level of 6 for the rad-hard NG-ULTRA FPGA and supports multicore software programming and FPGA acceleration.
      The talk will focus on the latest developments and results obtained by Bambu high-level synthesis tool on the HERMES project's use cases. Specifically, the presentation will highlight how Bambu optimizes specific patterns common in the HERMES use cases.

      Speaker: Fabrizio Ferrandi (Politecnico di Milano)
    • 15
      XNG versus bare-metal performance on NG-Ultra: a comprehensive comparison

      A comparison of the NG-Ultra high-level performance capabilities in both bare-metal and under the XNG hypervisor for NG-Ultra both in a monocore and in a multicore environment will be carried out, providing valuable insights into a high-degree optimization and unlocking the full potential of this hardware.

      Speaker: Antonio García Vilanova (FentISS)
    • 1:00 PM
      Lunch Break
    • 16
      GMV and BRAVE FPGAs: From Studies to Flight Hardware use
      Speaker: Rubén Domingo Torrijos (GMV)
    • 17
      SYSGO, PikeOS and NG-ULTRA compatibility

      A brief introduction of SYSGO and its flagship product PikeOS for MPU will be presented, following by a description of the current functionalities available with PikeOS for MPU on the NG-ULTRA development kit platform from NanoXplore: runtime features, as well as development tooling supported. In addition, a live demonstrator featuring PikeOS for MPU running on each of the 4 cores of the NG-Ultra platform will be demonstrated.

      Speaker: Mr Thierry Maudire (SYSGO S.A.S.)
    • 3:30 PM
      Thanks and Farewells